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Interrupt mode and polarity selection
The GPIO module provides two interrupt modes to set the interrupt flags: edge trigger mode and level trigger
mode. The interrupt mode for each FPT line can be selected using SEPTn/GPIO_FPTnn_MOD register.
When SEPTn bit is set to 1 (default), the corresponding port is set to edge trigger mode. In edge trigger mode,
the interrupt flag is set at the active edge of the input signal and it retains 1 until reset via software.
When SEPTn is set to 0, the corresponding port is set to level trigger mode. In level trigger mode, the interrupt
flag is set when the input signal goes the active level and it retains 1 until reset via software.
SLEEP mode can be canceled by causing a port input interrupt regardless of how the GPIO interrupt mode (edge
trigger/level trigger) is set.
The active level/edge of the input signal can be selected using SPPTn/GPIO_FPTnn_POL register.
When SPPTn is set to 1 (default), high level (in level trigger mode) or rising edge (in edge trigger mode) is se-
lected.
When SPPTn is set to 0, low level (in level trigger mode) or falling edge (in edge trigger mode) is selected.
Interrupt flags
The port interrupt circuit provides 16 interrupt flags (SFGPn/GPIO_FPTnn_FLG register) corresponding to the
FPT interrupt ports.
In level trigger mode, the interrupt flag is set according to the input signal level.
In edge trigger mode, the interrupt flag is set at the active edge of the input signal.
The interrupt flag must be reset by writing 1 after an interrupt occurs.
Interrupt enable bits
Each FPT interrupt port can be enabled or disabled to generate interrupts using the corresponding interrupt en-
able bit (SIETn/GPIO_FPTnn_MSK register).
To use port input interrupts, the interrupt port pins must be configured as an I/O port using the corresponding
port function select bits. Before setting SIETn to 1, the corresponding SFGPn must be cleared to 0.
To enable interrupts, set SIETn to 1. To disable interrupts, set SIETn to 0.
When SFGPn is set to 1 while the corresponding SIETn is set to 1, an interrupt request signal is output to the
ITC. An interrupt is generated if the ITC and C33 PE Core interrupt conditions are satisfied.
For specific information on interrupt processing, see the "Interrupt Controller (ITC)" chapter.
DMA trigger
An FPT interrupt port can be selected as a DMA trigger source using the SPTRG[3:0]/GPIO_DMA register.
SPTRG[3:0]
0xf
0xe
0xd
0xc
0xb
0xa
0x9
0x8
The interrupt signal of the selected FPT line, which is generated according to the interrupt mode and polarity
settings regardless of the SIETn setting (even if the interrupt is disabled), is sent to the DMAC to trigger a DMA
transfer. For more information on DMA transfer, see the "DMA Controller (DMAC)" chapter.
S1C33L26 TECHNICAL MANUAL
Table 24.
5.5 Port input Interrupt Conditions
SEPTn
SPPTn
1
1
1
0
0
1
0
0
Table 24.
5.6 DMA Trigger Source Selection
Trigger source
FPTF
FPTE
FPTD
FPTC
FPTB
FPTA
FPT9
FPT8
Seiko Epson Corporation
Port input interrupt condition
Rising edge input
Falling edge input
High level input
Low level input
SPTRG[3:0]
Trigger source
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
24 I/O PORTS (GPIO)
FPT7
FPT6
FPT5
FPT4
FPT3
FPT2
FPT1
FPT0
(Default: 0x0)
24-7
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