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Figure 24-44. MMC/SD/SDIO Controller Command Transfer Flow With Interrupts
interrupt occurs
Read the MMCi.MMCHS_STAT
register
CTO = 0x1
and
CCRC = 0x1
Yes
Set MMCi.MMCHS_SYSCTL[25] SRC
bit to 0x1 and wait until it returns to 0x0
Return
24.5.2.7.2 MMCHS Clock Frequency Change
Figure 24-45
describes the different steps that allow to change the MMC/SD/SDIO output clock frequency.
SWPU177N – December 2009 – Revised November 2010
Public Version
Start
Read the MMCi.MMCHS_PSTATE[0]
CMDI bit
CMDI = 0x0
Yes
The command line is not in use;
Issuing a command is allowed
Write MMCi.MMCHS_CON register; set
MIT, STR bit fields
Write MMCi.MMCHS_CSRE register, if
response type permits
(see standard specifications)
Write MMCi.MMCHS_BLK
Write MMCi. MMCHS_SYSCTL to
set DTO bitfield.
Write MMCi.MMCHS_ARG register
Write MMCi.MMCHS_IE and
MMCi. MMCHS_ISE registers to
enable required interrupts
Write MMCi.MMCHS_CMD register
wait for interrupt
No
CC = 0x1
CMD with response ?
No
No response
Read MMCi.MMCHS_RSP register
Copyright © 2009–2010, Texas Instruments Incorporated
MMC/SD/SDIO Basic Programming Model
No
The command line is in use;
Issuing a command is not allowed
Bitfields in MMCHS_CON should be
configured according to command features
(stream or multiblock, with or without timeout)
MMCHS_BLK must be configured with
block size and number of blocks if data
are present.
In order to use interrupts
MMCHS_ISE must be configured.
If polling is used configuring MMCHS_IE
is enough.
No
Yes
Interrupt
handler
Yes
A response is waiting
MMC/SD/SDIO Card Interface
mmchs-041
3409
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