Independent Analog Peripherals Supply; Figure 2. Stm32U575Xq And Stm32U585Xq Power Supply Overview (With Smps) - ST STM32U575 Series Application Note

In devices without SMPS, the I/Os and system analog peripherals (such as PLLs and reset block) are fed by V
supply source. The V
Note: If the selected package has the SMPS step-down converter option but the SMPS is not used by the application
(and the embedded LDO is used instead), it is recommended to set the SMPS power supply pins as follows:
• VDDSMPS and VLXSMPS connected to VSS
• VDD11 pins connected to VSS through two 2.2 µF capacitors as in normal mode
2.1.1

Independent analog peripherals supply

To improve ADC and DAC conversion accuracy and to extend the supply flexibility, the analog peripherals have
an independent power supply that can be separately filtered and shielded from noise on the PCB.
The voltage supply input of the analog peripherals is available on a separate VDDA pin. An isolated supply
ground connection is provided on VSSA pin.
The V supply voltage can be different from V
DDA
logically and electrically isolated and therefore are not available. The isolation must be removed before using
these peripherals, by setting the ASV bit in the PWR_SVMCR register, once the V
The V supply can be monitored by analog voltage monitors (AVM), and compared with two thresholds
DDA
(1.6 V for AVM1 or 1.8 V for AVM2). For more details, refer to the device datasheet and section 'Peripheral
voltage monitoring (PVM)' of the reference manual.
When a single supply is used, the VDDA pin can be externally connected to the same V
external filtering circuit, in order to ensure a noise-free V
AN5373 - Rev 1
Figure 2. STM32U575xQ and STM32U585xQ power supply overview (with SMPS)
VDDA
VSSA
VDDUSB
VSS
VDDIO2
VSS
VSS
VDD
2x VDD11
VLXSMPS
VDDSMPS
VSSSMPS
VBAT
power supply for digital peripherals and memories is generated from the LDO.
CORE
V domain
DDA
2 x A/D converters
2 x comparators
2 x D/A converters
2 x operational amplifiers
Voltage reference buffer
USB transceiver
V domain
DDIO2
V
DDIO2
I/O ring
PG[15:2]
V domain
DD
V
DDIO1
I/O ring
Reset block
Temperature sensor
3 x PLL
Internal RC oscillators
Standby circuitry
(Wakeup logic, IWDG)
Voltage regulator
LDO regulator
V
CORE
SMPS regulator
Low-voltage detector
Backup domain
LSE crystal 32kHz oscillator
Backup registers
RCC_BDCR register
RTC
TAMP
BKPSRAM
. After reset, the analog peripherals supplied by V
DD
reference voltage.
DD
AN5373
Power supplies
V domain
CORE
Core
SRAM1
SRAM2
SRAM3
SRAM4
Digital
peripherals
Flash memory
DDA
supply is present.
DDA
supply, through an
DD
DD
are
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