Other Signals; Unused I/Os And Features; Figure 11. Typical Layout For Vdd/Vss Pin Pair - ST STM32U575 Series Application Note

The figure below shows the typical layout of such a VDD/VSS pin pair.
7.5

Other signals

When designing an application, the EMC performance can be improved by closely studying the following:
• Signals for which a temporary disturbance affects the running process permanently (it is the case for
interrupts and handshaking strobe signals but not the case for LED commands)
For these signals, a surrounding ground trace, shorter lengths, and the absence of noisy and sensitive
traces nearby (crosstalk effect) improve EMC performance.
For digital signals, the best possible electrical margin must be reached for the two logical states. Slow
Schmitt triggers are recommended to eliminate parasitic states.
• Noisy signals (example: clock)
• Sensitive signals (example: high impedance)
7.6

Unused I/Os and features

All microcontrollers are designed for a variety of applications and often a particular application does not use
100 % of the MCU resources.
To increase the EMC performance and avoid extra power consumption, the unused features of the device must
be disabled and disconnected from the clock tree, as follows:
• The unused clock source must be disabled.
• The unused I/Os must not be left floating.
• The unused I/O pins must be configured as analog input by software, and must be connected to a fixed logic
level 0 or 1 by an external or internal pull-up or pull-down, or configured as output mode using software.
AN5373 - Rev 1
Figure 11. Typical layout for VDD/VSS pin pair
Via to VDD
VDD VSS
STM32
Via to VSS
AN5373
Other signals
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