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ST STM32U3 Application Note

ST STM32U3 Application Note

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AN6011
Application note
Getting started with STM32U3 MCU hardware development
Introduction
This application note is intended for system designers who require a hardware implementation overview of the development
board features: power supply, clock management, reset control, boot mode settings, and debug management.
It details how to use the STM32U3 series microcontrollers (named STM32U3) and describes the minimum hardware resources
required to develop an application using these MCUs.
This document also includes detailed reference design schematics with the description of the main components, interfaces, and
modes.
AN6011 - Rev 1 - February 2025
www.st.com
For further information, contact your local STMicroelectronics sales office.

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  • Page 1 This application note is intended for system designers who require a hardware implementation overview of the development board features: power supply, clock management, reset control, boot mode settings, and debug management. It details how to use the STM32U3 series microcontrollers (named STM32U3) and describes the minimum hardware resources required to develop an application using these MCUs.
  • Page 2 AN6011 General information General information ® ® This document applies to the STM32U3 series Arm Cortex -M33 core-based microcontrollers. Note: Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere. Reference documents ® Reference manual STM32U3 series Arm...
  • Page 3 – The SMPS power supply pins (VLXSMPS, VDD11, VDDSMPS, VSSSMPS) are available only on packages with SMPS. In such packages, the STM32U3 devices embed two regulators, one LDO and one SMPS in parallel, to provide the V supply to digital peripherals. A 4.7 μF total external CORE capacitor and a 2.2 µH coil are required on VDD11 pins.
  • Page 4 When the VREF+ pin is double-bonded to VDDA in a package, the internal VREFBUF is not available, and must be kept disabled. must always be equal to V REF- The following figures present an overview of the STM32U3 devices power supply, depending on the SMPS presence. Figure 1. STM32U375xx and STM32U385xx power supply overview (without SMPS)
  • Page 5 AN6011 Power supply management Figure 2. STM32U375xxxxQ and STM32U385xxxxQ power supply overview (with SMPS) domain A/D converters VDDA Comparators D/A converters VSSA Operational amplifiers Voltage reference buffer VDDUSB USB transceiver domain DDIO2 DDIO2 VDDIO2 I/O ring PG[15:2] domain DDIO1 I/O ring Reset block domain CORE...
  • Page 6 AN6011 Power supply management ADC and DAC reference voltage To ensure a better accuracy on low-voltage inputs and outputs, the user can connect to VREF+ pin, a separate reference voltage lower than V is the highest voltage, represented by the full-scale value, for an analog input (ADC) or output (DAC) REF+ signal.
  • Page 7 (range 1/2), in all Stop modes (Stop 0/1/2/3), and in Standby mode with SRAM2. Refer to the Low-power mode summary table in document [1]. The STM32U3 devices without SMPS embed only the LDO regulator that controls all voltage-scaling ranges and power modes.
  • Page 8 AN6011 Power supply management Caution: The EPOD (embedded power distribution) booster must be enabled and ready before increasing the system clock frequency above 24 MHz in Range 1 and Range 2 (refer to document for sequences to switch between voltage scaling ranges). 2.1.6 Power supply for I/O analog switches Some I/Os embed analog switches for both analog peripherals (ADCs, COMPs, DACs) and TSC (touch sensing...
  • Page 9 AN6011 Power supply management The figures below details the power supply schemes for packages with and without SMPS. Figure 3. Power supply scheme for STM32U375/385xxxxQ (with SMPS) VBAT 1.65 – 3.6 V Backup circuitry (LSE, RTC, TAMP, backup registers) 3.3 V Power switch VDDUSB 100 nF...
  • Page 10 AN6011 Power supply management Figure 4. Power supply scheme for STM32U375/385xx (without SMPS) VBAT 1.65 – 3.6 V Backup circuitry (LSE, RTC, TAMP backup registers) 3.3 V VDDUSB 100 nF VCAP Power switch 4.7 µF CORE n x VDD CORE regulator DDIO1 Kernel logic...
  • Page 11 AN6011 Power supply management To avoid leakage currents between the available supplies and V (or ground), V must be provided first to the MCU, and then released with tolerance during power down (see Particular conditions during the power-down phase). 2.3.2 General requirements During power-up and power-down phases, the following power sequence requirements must be respected: •...
  • Page 12 AN6011 Power supply management Reset and power-supply supervisor 2.4.1 Brownout reset (BOR) The devices have a brownout reset (BOR) circuitry. The BOR is active in all power modes except Shutdown mode, and cannot be disabled. The BOR monitors the backup domain supply voltage that is V when present, otherwise.
  • Page 13 AN6011 Power supply management Figure 7. Simplified diagram of the reset circuit System reset External Filter reset NRST WWDG reset IWDG reset Pulse Software reset generator Low-power manager reset (min 20 μs) Option byte loader reset 2.4.3 Backup domain reset A backup domain reset is generated when one of the following events occurs: •...
  • Page 14 Smaller packages usually provide better signal integrity. This is further enhanced as small-pitch and high‑ball density requires multilayer PCBs that allow better supply/ground distribution. • Compatibility with other devices Table 1. Package summary for STM32U3 devices Package Height (mm) Size (mm) Pitch (mm) LQFP48 SMPS 7 ×...
  • Page 15 AN6011 Packages Pinout summary Table 2. Pinout summary for STM32U3 packages (with SMPS) packages (without SMPS) Pin name Specific I/Os PC14- OSC32_IN PC15- OSC32_OUT PH0-OSC_IN PH1-OSC_OUT System pins NRST PH3-BOOT0 PB7-BOOT0 Power pins VBAT VDDUSB VSSA VREF- VREF+ VDDA VDDIO2...
  • Page 16 AN6011 Packages Caution: STM32U3 packages with and without SMPS are not compatible for almost all power supply pins of Table Example: The pin number 32 on LQFP64 SMPS package is VSS, while on LQFP64 without SMPS it is VDD. It means that the system is short-circuited when a legacy package is mounted on an SMPS socket.
  • Page 17 AN6011 Clocks Clocks The following clock sources can be used to drive the system clock (SYSCLK): • HSI16: high-speed internal 16 MHz RC oscillator clock • MSIS: multi-speed internal RC oscillator clock, from 3 to 96 MHz • HSE: high-speed external crystal or clock, from 4 to 50 MHz •...
  • Page 18 AN6011 Clocks 4.1.2 External source (HSE bypass) In this mode, an external clock source must be provided. This mode is selected by setting the HSEBYP and HSEON bits in the RCC_CR. The external clock signal with ca. 40-60 % duty cycle depending on the frequency (refer to the datasheet) must drive the OSC_IN pin while the OSC_OUT pin can be used as a GPIO (see Table The bypass mode is optimized for square input signals when HSEEXT = 1.
  • Page 19 AN6011 Boot configuration Boot configuration Boot mode selection At start-up, nBOOT0 and nSWBOOT0 option bits of the FLASH_OPTR register, and ADD[24:0] option bytes of the FLASH_BOOT0R, FLASH_BOOT1R or FLASH_SBOOT0R registers are used to select the boot memory address that includes: •...
  • Page 20 The table below details the boot modes when the TrustZone is enabled. ® Table 5. Boot modes when TrustZone is enabled (TZEN = 1) BOOT_ BOOT0 Boot address option‑byte ST programmed nBOOT0 Boot area LOCK BOOT0 command selection default value Secure boot base address 0...
  • Page 21 AN6011 Debug management Debug management ® ™ The serial wire/JTAG debug port (SWJ-DP) is an Arm standard CoreSight debug port. The host/target interface is the hardware equipment that connects the host to the application board. This interface is made of three components: a hardware debug tool, a serial-wire connector, and a cable connecting the host to the debug tool.
  • Page 22 AN6011 Debug management 6.2.2 Flexible SWJ-DP pin assignment After reset (SYSRESETn or PORESETn), all five pins used for the SWJ-DP are assigned as dedicated pins that are immediately usable by the debugger host. Note: The trace outputs are not assigned except if explicitly programmed by the debugger host. The table below shows the different possibilities for releasing some pins (refer to document for more details).
  • Page 23 SWD port connection with standard JTAG connector The figure below shows the connection between the device and a standard JTAG connector. Figure 9. JTAG connector implementation JTAG connector Connector 2 x 10 STM32U3 MCU VTREF nJTRST nTRST JTDI JTMS/SWDIO JTCK/SWCLK...
  • Page 24 AN6011 Design recommendations Design recommendations PCB (printed circuit board) For technical reasons, it is best to use a multilayer PCB, with a separate layer dedicated to ground (V ) and another dedicated to the V supply. This provides a good decoupling and a good shielding effect. For many applications, economical reasons prohibit the use of this type of board.
  • Page 25 AN6011 Design recommendations The figure below shows the typical layout of such a VDD/VSS pin pair. Figure 10. Typical layout for VDD/VSS pin pair Via to VDD Via to VSS STM32 Other signals When designing an application, the EMC performance can be improved by closely studying the following: •...
  • Page 26 Description The reference design shown in the following figures is based on an STM32U3 device in LQFP100. This reference design can be tailored to any STM32U3 device with a different package, refer to the pinout/ballout section of the device datasheet.
  • Page 27 AN6011 Reference design Design reference for a STM32U3 device (with and without SMPS) The table below lists the components used for a STM32U3 design reference: • based on STM32U375/385xxxxQ device, with SMPS (see Figure • including on STM32U3xxxx device, without SMPS (see Figure Table 9.
  • Page 28 AN6011 Reference design Figure 11. STM32U375/385xxxxQ reference design (with SMPS) AN6011 - Rev 1 page 28/38...
  • Page 29 AN6011 Reference design Figure 12. STM32U3xxxx reference design (without SMPS) AN6011 - Rev 1 page 29/38...
  • Page 30 Power supply decoupling An adequate power decoupling for STM32U3 devices is necessary to prevent an excessive power noise and ground bounce noise. Refer to Section 2.2: Power supply schemes for more details.
  • Page 31 The total bus CARD capacitance is C + N*C where the host is an STM32U3 device, bus is all the signals and Host Card card is an SD card. AN6011 - Rev 1...
  • Page 32 AN6011 Recommended PCB routing guidelines 9.4.2 Octal serial peripheral interface (OCTOSPI) Interface connectivity The OCTOSPI is a specialized communication interface targeting single, dual , quad or octo-SPI flash memories. The OCTOSPI interface is a serial data bus interface, that consists of a clock (CLK), a chip select signal (nCS), clock to support 1.8V HyperBus protocol (nCLK), line for data strobe/write mask signals to/from the memory (DQS), and eight data lines (IO[0:7]).
  • Page 33 AN6011 Revision history Table 10. Document revision history Date Version Changes 05-Feb-2025 Initial release. AN6011 - Rev 1 page 33/38...
  • Page 34 AN6011 Contents Contents General information ............. . . 2 Power supply management .
  • Page 35 Description ..............26 Design reference for a STM32U3 device (with and without SMPS) ....27 Recommended PCB routing guidelines .
  • Page 36 Components of STM32U3 reference design ........
  • Page 37 AN6011 List of figures List of figures Figure 1. STM32U375xx and STM32U385xx power supply overview (without SMPS) ......4 Figure 2.
  • Page 38 ST’s terms and conditions of sale in place at the time of order acknowledgment. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of purchasers’...