Power Supply Sequence Between Vdda, Vddusb, Vddio2, And Vdd; Power Supply Isolation; General Requirements; Particular Conditions During Power-Down Phase - ST STM32U575 Series Application Note

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Table Of Contents

Table of Contents

2.3

Power supply sequence between V

2.3.1

Power supply isolation

The devices feature a powerful reset system that ensures the main power supply (V

operating range before releasing the MCU reset.

This reset system is also in charge of isolating the independent power domains: V

. This reset system is supplied by V

worse-case conditions).

In order to avoid leakage currents between the available supplies and V

to the MCU and released last with tolerance during power down (refer to

2.3.2

General requirements

During power-up and power-down phases, the following power sequence requirements must be respected:

•

When V

+ 300 mV.

•

When V

DD_MAX

DD_MIN

Note:

is an independent supply and has no constraint versus V

BAT

2.3.3

Particular conditions during power-down phase

During the power-down phase, V

to the MCU remains below 1 mJ. This allows external decoupling capacitors to be discharged with different time

constants during the power-down transient phase (refer to

, V

DDX

DDA

Note:

During the power-down transient phase, V

AN5373 - Rev 1

and is not functional before V

is below 1 V, other power supplies (V

is above 1 V, all power supplies are independent.

Figure 5.

0.3

Power-on

Invalid supply area

< V

+ 300 mV

DDX

(1) V

refers to any power supply among V

DDX

can temporarily become lower than other supplies only if the energy provided

, or V

) power rails must be switched off before V

DDIO2

DDUSB

DDX