Clocks - Xilinx FMC XM105 User Manual

FMC XM105 Debug Card User Guide
UG537 (v1.2) September 24, 2010
Downloaded from Elcodis.com electronic components distributor

14. Clocks

Two clock sources (Table
applications:
• Differential SMA connectors
• Si570 IIC LVDS clock
A pair of differential SMA connectors can be utilized to provide a high-precision
differential clock or a single-ended clock to the board. Virtex-6 FPGA and Spartan-6 FPGA
devices require single-ended clocks on the "P" input of an IOB pair. See Xilinx FPGA
documentation for additional information.
Consult Xilinx FMC- supported board user guide for interface voltages, I/O standard
support on FPGA clock pins; and to determine LVDS input clock termination
requirements, either on the printed-circuit board or using an IBUFGDS primitive for FPGA
on-chip termination.
Table 1-14: Clock Sources Routed to Mezzanine FMC HPC J17 Connector
FMC HPC
Connector J17 Pin
H4
H5
G2
G3
Notes:
1. Clock sources are available for FMC LPC and FMC HPC board
applications.
2. The Si570 provides a LVDS output clock.
A Silicon Labs Si570 IIC programmable clock source provides a low-jitter clock with a user-
programmable output frequency from 10 to 810 MHz. As shipped, the CLK0_M2C clock
frequency is 156.25 MHz. The component installed on the XM105 is factory programmed
with parameters in Table
Table 1-15: Characteristics of Si570 Component
Si570 Characteristic
Output Format
Output Enable Polarity
Temperature Stability
Frequency Range
Six-Digit Startup
Power Supply
IIC Address
For additional information on this component, including reprogramming the clock
frequency through the IIC serial bus interface, consult the Silicon Labs Si570 Data Sheet at
https://www.silabs.com.
1-14) are provided for FMC LPC and FMC HPC board
Signal Name Source
(2)
CLK0_M2C_P Si570 U2 pin 4
(2)
CLK0_M2C_N Si570 U2 pin 5
CLK1_M2C_P
CLK1_M2C_N SMA J10
1-15.
www.xilinx.com
Board Technical Description
(1)
SMA J9
XM105
LVDS
High
50 ppm
10–810 MHz
156.250 MHz
3.3V
x5D
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