Xilinx FMC XM105 User Manual page 12

Chapter 1: XM105
Table 1-2: XM105 Features (Cont'd)
Number
9 40-pin header
10 40-pin header
11 40-pin header
12 Mictor connector
13 9-pin header
14 Clocking
15 2 Kb EEPROM
16 Power Good LEDS
17 2-pin header
Notes:
1. Available only with FMC HPC board interfaces. Xilinx Virtex-6 FPGA ML605 evaluation board provides one FMC LPC and one
FMC HPC interface. Xilinx Spartan-6 FPGA SP601 and SP605 evaluation boards provide a single FMC LPC interface.
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Feature
(1)
J2: 20 pin x 2 row male header
J1: 20 pin x 2 row male header
(1)
J3: 20 pin x 2 row male header
P1: 38 pin female Mictor connector
J19: 9 pin x 1 row male header with Mictor JTAG pins connected
between J19 and P1
SMA connectors (J9, J10) and Silicon Labs Si570 IIC serial bus
reprogrammable LVDS clock source
IIC compatible electrically erasable programmable memory
(EEPROM) with 2 Kb (256 bytes) of non-volatile storage.
Power good LEDS for +12V, board to mezzanine card (PG_C2M) and
V /3.3V
adjust
J18: 2 pins x 1 male header for GND connection to PG_M2C LPC
connector.
Notes
www.xilinx.com
Schematic
Page
FMC XM105 Debug Card User Guide
UG537 (v1.2) September 24, 2010
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