Kb Eeprom - Xilinx FMC XM105 User Manual

Chapter 1: XM105
28
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15. 2-Kb EEPROM

A ST Microelectronics M24C02 2-Kb serial IIC bus EEPROM component provides a small
amount of non-volatile memory storage on the XM105.
The IIC address of this component is controlled by a combination of the specific board
interface and chip enable connections to the component inputs on the XM105. Signals GA0
and GA1 from the board are connected to the chip enable inputs of the M24C02 component
enables E0 and E1. As shown in
strapping to 3.3V and GND signals, which creates a different E0 and E1 chip enable decode
on the E1 and E0 inputs of the EEPROM.
The IIC memory addressing protocol requires a bus master to initiate communication to a
peripheral device using a start condition followed by a device select code. The device select
code consists of a 4-bit Device Type Identifier and a 3-bit Chip Enable Address (E2, E1, E0).
Bit 0 is used to indicate read/write. The Device Type Identifier for the EEPROM is 1010
binary. Table 1-17 shows the generic EEPROM Device Select Code as well as specific
Device Code Select addresses for the EEPROM when the XM105 is connected to boards
defined in Table 1-1, page
Table 1-16: M24C02 Enable Input Connections
FMC HPC
M24C02 Chip Control
Enable Input Signal
Connection
E0 GA1
E1 GA0
E2 GND
Table 1-17: EEPROM IIC Device Select Code
Bit 7:4
Device Type Bit 3 Bit 2 Bit 1
Identifier
E2
1010
0
1010
0
1010
0
1010
0
1010
0
1010
Table 1-16, Xilinx boards provide GA0 and GA1 signal
8.
SP601 LPC SP605 LPC
Connector
GND
3.3V
GND
Bit 0 (LSB)
E1 E0 Read/Write
GA0 GA1 Read/Write
1 0 Read/Write
1 0 Read/Write
0 1 Read/Write
0 0 Read/Write
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ML605 LPC
Connector Connector
GND 3.3V
3.3V GND
GND GND
Description
M24C02 Device Select Code
Connected to XM105
Connected to SP601 LPC interface
Connected to SP605 LPC interface
Connected to ML605 LPC interface
Connected to ML605 HPC interface
FMC XM105 Debug Card User Guide
UG537 (v1.2) September 24, 2010
ML605 HPC
Connector
GND
GND
GND