Board Technical Description - Xilinx FMC XM105 User Manual

Chapter 1: XM105

Board Technical Description

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The XM105 provides a number of multi-position headers and connectors which break out
the FPGA interface signals to and from the board interface. A serial IIC bus
reprogrammable LVDS clock source and a pair of SMA connectors provide differential
clock sources to the board FGPA. A 2-Kb serial IIC EEPROM is connected to the IIC
interface of the board providing non-volatile storage.
Figure 1-2 shows a block diagram of the XM105. The gray shaded blocks are only available
when the board interface is a high pin count board interface. All other interfaces are
available for low pin count board applications.
X-Ref Target - Figure 1-2
J2 Header
2 x 20
J3 Header
2 x 20
J23 Header
2 x 6
J5 Header
1 x 9
FMC JTAG
SMA J9, J10
LVDS Clock
2 Kb
EEPROM
Requires board with FMC HPC support.
www.xilinx.com
J1 Header
J20 Header
J16 Header
J17
FMC HPC
Interface
J15 Header
Mictor P1
38 Position
Power Good
Figure 1-2: XM105 Block Diagram
2 x 20
2 x 8
2 x 6
User
1 x 6
LEDs
J19 Head
1 x 9 JTAG
LEDs
UG537_02_110509
FMC XM105 Debug Card User Guide
UG537 (v1.2) September 24, 2010