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Connectors
OSC (O)
The 'oscillator' signal is a high-speed clock with a 70-nanosecond period (14.31818
MHz). This signal is not synchronous with the system clock. It has a 50% duty
cycle.
-REFRESH (I/O)
This signal is used to indicate a refresh cycle and can be driven by a microprocessor
on the I/O channel. This signal is active low.
-RESETIN (I)
This signal is used to provide an external reset signal to the system. It is an active
low signal.
-RSTDRV (O)
The 'reset drive' signal is used to reset or initialize system logic at power-up time or
during a low voltage condition. This signal is active low.
SA0 through SA16 (I/O)
Address signals 0 through 16 are used to address memory and I/O devices within the
system. These address lines, in addition to LA17 through LA23, allow access of up
to 16M of memory. SA0 through SA16 are gated on the system bus when 'buffered
address latch enable' signal (BALE) is high and are latched on the falling edge of
BALE. These signals are generated by the microprocessor or DMA controller. They
also may be driven by other microprocessors or DMA controllers that reside on the
I/O channel.
-SBHE (I/O)
The '-system bus high enable' signal indicates a transfer of data on the upper byte of
the data bus, SD8 through SD15. 16-bit deives use -SBHE to condition data bus
buffers tied to SD8 through SD15. This signal is active low.
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