RadiSys EPC-23 Hardware Reference Manual page 34

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SD0 through SD15 (I/O)
These signals provide bus bits 0 through 15 for the microprocessor, memory, and I/O
devices. D0 is the least-significant bit and D15 is the most-significant bit. All 8-bit
devices on the I/O channel should use D0 through D7 for communications to the
microprocessor. The 16-bit devices will use D0 through D15. To support 8-bit
devices, the data on D8 through D15 will be gated to D0 through D7 during 8-bit
transfers to these devices; 16-bit microprocessor transfers to 8-bit devices will be
converted to two 8-bit transfers.
-SMEMR (O) -MEMR (I/O)
These signals instruct the memory devices to drive data onto the data bus.
4 -SMEMR is active only when the memory decode is within the low 1M of memory
space. -MEMR is active on all memory read cycles. -MEMR may be driven by any
microprocessor or DMA controller in the system.
-MEMR and the decode of the low 1M of memory. When a microprocessor on the
I/O channel wishes to drive -MEMR, it must have the address lines valid on the bus
for one clock cycle before driving -MEMR active. Both signals are active low.
-SMEMW (O) -MEMW (I/O)
These signals instruct the memory devices to store the data present on the data bus. -
SMEMW is active only when the memory decode is within the low 1M of the
memory space. -MEMW is active on all memory write cycles. -MEMW may be
driven by any microprocessor or DMA controller in the system. -SMEMW is derived
from -MEMW and the decode of the low 1M of memory. When a microprocessor on
the I/O channel wishes to drive -MEMW, it must have the address lines valid on the
bus for one clock cycle before driving -MEMW active. Both signals are active low.
TC (O)
The 'terminal count' signal provides a high pulse when the terminal count for any
DMA channel is reached.
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EPC-23 Hardware Reference
-SMEMR is derived from