Table of Contents
Advertisement
4
Artisan Scientific - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisan-scientific.com
AEN (O)
The 'address enable' signal is used to degate the microprocessor and other devices
from the I/O channel to allow DMA transfers to take place. When this line is active,
the DMA controller has control of the address bus, the data-bus Read command lines
(memory and I/O), and the Write command lines (memory and I/O). This signal is
active high.
BALE (O) (buffered)
The 'buffered address latch enable' signal is provided by the Bus Controller and is
used to latch valid addresses and memory decodes from the microprocessor. It is
available to the I/O channel as an indicator of a valid microprocessor or DMA
4
address (when used with 'address enable' signal, AEN). Microprocessor addresses
SA0 through SA16 are latched with the falling edge of BALE. BALE is forced high
(active) during DMA cycles.
CLK (O)
This is the 8-MHz system 'clock' signal. It is a synchronous microprocessor cycle
clock with a cycle time of 125 nanoseconds. The clock has a 50% duty cycle. This
signal should be used only for synchronization. It is not intended for uses requiring a
fixed frequency.
-DACK0 through -DACK3, -DACK5, & -DACK6 (O)
-DMA acknowledge signals are used to acknowledge DMA requests. These signals
are active low.
DRQ0 through DRQ3, DRQ5, DRQ6 (I)
The 'DMA request' signals are asynchronous channel requests used by peripheral
devices and a microprocessor to gain DMA service (or control of the system). They
are prioritized, with DRQ0 having the highest priority and DRQ6 the lowest. A
request is generated by bringing a DRQ line to an active (high) level. A DRQ line is
held high until the corresponding 'DMA acknowledge' (DACK) line goes active.
DRQ0 through DRQ3 perform 8-bit DMA transfers, DRQ5 and DRQ6 perform 16-
bit transfers. DRQ4 is used on the system board and is not available on the I/O
channel.
Page 22
EPC-23 Hardware Reference
Advertisement
Table of Contents
