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Connectors
B-Row:
Pin
Signal
Pin
Signal
B1
GND
B16 GND
B2
(reserved)
B17 IRQ9
B3
GND
B18 IRQ6
B4
GND
B19 IRQ4
B5
SD14
B20 IRQ3
B6
SD12
B21 -RSTDRV
B7
SD10
B22 GND
B8
GND
B23 IOCHRDY
B9
SD8
B24 -0WS
B10 SD6
B25 -IOCS16
B11 SD4
B26 -MEMCS16 B41 LA18
B12 GND
B27 -REFRESH
B13 SD2
B28 GND
B14 SD0
B29 -IOW
B15 IRQ14
B30 -IOR
Table 10. EXM Expansion Card B-Row Pin-out.
EXM Expansion Connector Signals
The signal definitions below are listed in alphabetical order. Signal definitions
preceeded by a
are copied from the IBM AT Technical Reference Manual. Some
liberties have been taken to correct the definitions for use with the Intel486 SL chip
set and an 8 MHz bus speed.
-0WS (I)
The 'zero wait state' signal tells the microprocessor that it can complete the present
bus cycle without inserting any additional wait cycles. In order to run a memory
cycle to a 16-bit device without wait cycles, 0WS is derived from an address decode
gated with a Read or Write command. In order to run a memory cycle to an 8-bit
device with a minimum of two wait states, 0WS should be driven active one clock
cycle after the Read or Write command is active, and gated with the address decode
for the device. Memory Read and Write commands to an 8-bit device are active on
the falling edge of CLK. 0WS is active low and should be driven with an open
collector or tri-state driver capable of sinking 20 mA.
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Pin
Signal
Pin
Signal
B31 -SMEMW
B45 SA12
B32 -SMEMR
B46 (key)
B33 GND
B47 (key)
B34 -MEMW
B48 SA10
B35 -MEMR
B49 SA8
B36 BALE
B50 GND
B37 CLK
B51 SA6
B38 GND
B52 SA4
B39 LA22
B53 SA2
B40 LA20
B54 SA0
B55 GND
B42 SA16
B56 GND
B43 GND
B57 -EXTSMI
B44 SA14
B58 GND
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