Introduction; Description; Board Features; Reference Designs - Avnet Xilinx Zynq 7Z045 Manual

1 Introduction

The purpose of this manual is to describe the functionality and contents of the Zynq 7Z045 Mini-Module
Plus Development Kit from Avnet Electronics Marketing. This document includes instructions for operating
the board, descriptions of the hardware features and explains out-of-the-box design code programmed in
the on-board QSPI flash.
1.1

Description

The Zynq Z7045 Mini-Module Plus Development Kit provides a complete hardware environment
for designers to accelerate their time to market. The kit delivers a stable platform to develop and
test designs targeted to the advanced Xilinx Zynq AP PSoC family. The installed Zynq Z7045
device offers a prototyping environment to effectively demonstrate the enhanced benefits of leading
edge Xilinx AP PSoC solutions. Reference designs are included with the kit to exercise standard
peripherals on the evaluation board for a quick start to device familiarization.
The Zynq Z7045 Mini-Module Plus Development Board is a SOM (System on a Module) that
requires mating it to a baseboard for access non-local peripherals and power. Currently the Zynq
Z7045 Mini-Module Plus is compatible with one Avnet designed baseboard.
Avnet Designed Baseboard
Mini-Module Plus Baseboard 2
1.2

Board Features

–
Zynq AP PSoC
–
Xilinx XC7Z045-1FFG900
–
I/O Connectors
–
Two (2) Mictor style connectors providing
132 user I/O signals and 8 Giga-bit
transceivers to the baseboard.
–
Multi-gigabit Serial transceivers (GTX)
–
Eight (8) GTX ports
–
Memory
–
1 GB DDR3 SDRAM components
(2 banks of 256 MB x 16)
–
128 MB Parallel Flash (x16)
–
32 MB QSPI Flash
–
2
8 KB I
–
Micro SD Card
1.3

Reference Designs

Reference designs that demonstrate some of the potential applications of the Zynq Z7045 Mini-
Module Plus Development Kit can be downloaded from the Avnet Design Resource Center
(www.em.avnet.com/MMP-7Z045-G). The reference designs include all of the source code and
project files necessary to implement the designs. See the PDF document included with each
reference design for a complete description of the design and detailed instructions for running a
demonstration on the development board. Check the DRC periodically for updates and new designs.
C EEPROM
Avnet Orderable Part Number
AES-MMP-BB2-G
–
Communication
–
Configuration
–
Other
Page 8
–
USB-UART
–
USB 2.0
–
10/100/1000 Ethernet
–
32 MB QSPI Flash
–
Micro SD Card
–
JTAG via baseboard
–
Programmable LVDS clock source
–
Processor PJTAG port
–
XADC header
–
2
Real-time clock (I C)