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Avnet RFSoC Getting Started Manual

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RFSoC Development Kit
Getting Started Guide
Version 1.6
November 26, 2019
© 2017 Avnet. All rights reserved. All trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
NOTICE OF DISCLAIMER: Avnet is providing this design, code, or information "as is." By providing the design, code, or information as one possible implementation of this feature,
application, or standard, Avnet makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you may
require for your implementation. Avnet expressly disclaims any warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any warranties
or representations that this implementation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose.

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Summary of Contents for Avnet RFSoC

  • Page 1 © 2017 Avnet. All rights reserved. All trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. NOTICE OF DISCLAIMER: Avnet is providing this design, code, or information "as is." By providing the design, code, or information as one possible implementation of this feature, application, or standard, Avnet makes no representation that this implementation is free from any claims of infringement.

  • Page 2: Table Of Contents

    Contents Introduction ......................... 3 Avnet RFSoC Development Kit Overview ..............3 Objectives ........................4 Requirements ......................4 Tools Setup ......................... 5 Hardware Setup ......................6 Booting ZCU111 ......................9 Ethernet TCP/IP Connection to ZCU111 ................... 10 Qorvo Card Control ....................12 Experiment 1: Generating a CW Tone through the TX Path ........

  • Page 3: Introduction

    MathWorks and industry-leading RF components from Qorvo. We extend the functionality of the Xilinx Zynq UltraScale+ RFSoC ZCU111 Evaluation Kit by adding the Qorvo 2x2 Small Cell RF front-end card, plus native ®...

  • Page 4: Objectives

    Gain familiarity with the Avnet RFSoC Development Kit with Qorvo RF Front End  Use the Avnet RFSoC Explorer GUI to control the hardware, generate and acquire signals into MATLAB through the RF signal chains of the Qorvo card ...

  • Page 5: Tools Setup

    Tools Setup RFSoC Explorer installs easily in the MATLAB APPS tab without modifying your registry or other applications. 1. From MATLAB  Add-Ons, search for Avnet RFSoC Explorer and click install. 2. From MATLAB  Add-Ons, search for Communications Toolbox Support Package for Xilinx Zynq-Based Radio and click install.

  • Page 6: Hardware Setup

    Hardware Setup The Avnet RFSoC Development Kit includes the Xilinx Zynq ZCU111 Evaluation Kit. There are many jumpers and switches on the board, shipped with default states, which do not need to change for this tutorial. In the following steps we describe the minimal configuration. For a comprehensive setup guide,...
  • Page 7 TX to RX through the same card, hence the use of DPD observation path for this tutorial. For a comprehensive description of the functionality of the RF front-end, see Qorvo 2x2 Small Cell RF Front- end 1.8 GHz Card Hardware User Guide at www.avnet.com/rfsockit RFSoC Development Kit Getting Started Guide Page 7...
  • Page 8 Figure 6 – Qorvo card mounted on ZCU111 Figure 7 - Block diagram of Avnet RFSoC Development Kit RFSoC Development Kit Getting Started Guide Page 8...

  • Page 9: Booting Zcu111

    2. You should observe terminal output from U-Boot and then Linux output appear in the Tera Term window. After the final boot message ‘Server Init Done’, press enter to generate a carriage return and command-line prompt from ZCU111. RFSoC Development Kit Getting Started Guide Page 9...

  • Page 10: Ethernet Tcp/Ip Connection To Zcu111

    Set a static IP for your host PC's Local Ethernet adapter. Make sure your PC and the board are on the same subnet, gateway, etc. IP 192.168.0.106 Laptop Ethernet IP: Subnet 255.255.255.0 From the host PC, open a Windows command prompt and ping the ZCU111 board to verify Ethernet connectivity. C:\> ping 192.168.0.105 RFSoC Development Kit Getting Started Guide Page 10...
  • Page 11 From the host PC serial terminal connection to Linux running on the ZCU111, verify Ethernet connectivity by pinging your host PC. root@xilinx-zcu111-2018_2:~# ping 192.168.0.106 RFSoC Development Kit Getting Started Guide Page 11...

  • Page 12: Qorvo Card Control

    Processing System (PS) APU of the RFSoC. Commands sent from the PC through the USB_UART of ZCU111 are subsequently transferred to control registers on the Qorvo card via an SPI BUS. Refer to the Avnet Qorvo 2x2 Small Cell RF Front-end 1.8GHz Card Hardware User Guide for more information.
  • Page 13 PA through the DPD observation path on channel 1 of the Qorvo card to the RF-ADC of RFSoC on ZCU111. This is done for the purpose of calibrating the DPD observation path RF-ADC in next steps.

  • Page 14: Experiment 1: Generating A Cw Tone Through The Tx Path

    PA. In this experiment we shall generate a CW tone in the digital domain from the RFSoC Explorer graphical user interface (GUI) running under MATLAB on the host PC. The digital signal data will be downloaded to the ZCU111 over TCP/IP and stored in DDR4 memory dedicated to the RF-DACs.

  • Page 15: Frequency Planning

    Block Figure 12 - Channel map of ZCU111 data converters From the main tab of RFSoC Explorer set the Board IP Address that was previously found using the ifconfig command from the host PC serial terminal connection to Linux running on the ZCU111.
  • Page 16 D yields a suitable sampling rate for the RF-ADC. s_ADC D = 8 ≥ 750 MHz s_ADC Table 41: Decimation Filter Operating Modes, Xilinx PG269 (v2.1) May 22, 2019 Ref: RFSoC Development Kit Getting Started Guide Page 16...
  • Page 17 Referring to Figure 14, a 1.00 MHz CW tone x(n) generated in the digital domain by RFSoC Explorer is sent through the interpolation filters and shifted in frequency by the complex mixer in the digital up-converter to form an analytic signal tone at 1843 MHz. Once converted to the analog domain the signal connects to the transmit path of the Qorvo card to reach the PA, where it is routed back through a directional coupler to an RF-ADC within the observation path normally used for PA linearization.

  • Page 18: Configuring The Rf-Adc In The Dpd Observation Path

    We start by enabling the ADC block for the DPD observation path in channel 1 of the Qorvo RF card, which connects to ADC07 (Tile 3, Block 1) of the RFSoC device on ZCU111. 1. Enable ADC Tile 3 in RFSoC Explorer. Click to enter the tile.
  • Page 19 DC. This is sometimes referred to as sub-sampling, as described on page 48 of Zynq UltraScale+ RFSoC RF Data Converter 2.1 PG269; see endnote v. Set the ADC complex mixer to -1842 MHz. Figure 18 - Setting ADC complex mixer frequency RFSoC Development Kit Getting Started Guide Page 19...
  • Page 20 Observe the information dialog confirming the 'effective’ NCO frequency. Refer also to Figure 14. Each of the RF-ADCs in the Zynq UltraScale+ RFSoC is built on multiple sub-ADCs in an interleaving architecture. The nature of the interleaving process requires that an intricate calibration algorithm be carried out to obtain the best dynamic range performance from the RF-ADC.
  • Page 21 Figure 19 - Configuring the RF-ADC RFSoC Development Kit Getting Started Guide Page 21...
  • Page 22 5. The configuration process communicates with the Xilinx RFdc Linux driver API running on the Processing System (PS) APU of the RFSoC, providing runtime interaction and monitoring of the data converters. For reference, the Xilinx RFdc source files are publicly available on GitHub RFdc responds with the actual ADC tile sampling frequency that was programmed in the internal PLL.

  • Page 23: Configuring The Rf-Dac In The Transmit Path

    Configuring the RF-DAC in the transmit path 1. Enable DAC Tile 1 in RFSoC Explorer. Click to enter the tile. 2. Enable RF-DAC block 2, connecting to channel 1 transmit path of the Qorvo RF card. Refer to Figure 10...
  • Page 24 DAC output sampling rate, post-mixer. Finally press ‘Configure’, then ‘Download’ to transfer the signal data from MATLAB to the DAC memory buffer of ZCU111. RFSoC Development Kit Getting Started Guide Page 24...
  • Page 25 6. Return to the main tab and descend into ADC Tile 3. Select ‘Single Capture’ and press ‘Acquire’. Observe the CW tone which has been mixed back to 1 MHz by the ADC mixer. The signal level is low because the digital attenuators are still at maximum attenuation. RFSoC Development Kit Getting Started Guide Page 25...
  • Page 26 Figure 21 - Channel 1 Tx Attenuator relaxed by 1.65 dB to reach 0 dBFS at observation ADC Important: Increasing the signal strength through the DPD observation path beyond this level may cause damage to the RF-ADC. This completes experiment 1. RFSoC Development Kit Getting Started Guide Page 26...

  • Page 27: Experiment 2: Generating An Lte Signal Through The Tx Path

    PA. In this experiment we shall generate an LTE standard-compliant signal in the digital domain from the RFSoC Explorer graphical user interface (GUI) running under MATLAB on the host PC. The digital signal data will be downloaded to the ZCU111 over TCP/IP and stored in DDR4 memory dedicated to the RF-DACs.
  • Page 28 Figure 23 - MathWorks LTE Downlink R.9 Reference Channel Waveform Next, use the Export dropdown menu in the top ribbon to select Export to RFSoC Explorer Figure 24 - Export Waveform Generator Signal to RFSoC Explorer At the information dialog select ‘Yes’ to maximize the signal level to the full available dynamic range for the DAC.
  • Page 29 Set interpolation factor to 8X. Set the complex mixer frequency to 1842 MHz. (See Figure 20) Press ‘Configure’ to send the DUC parameters to the RFSoC RF Data Converter subsystem. Press ‘Download’ to transfer the signal data from MATLAB to the DAC memory buffer of ZCU111.
  • Page 30 5. The ADC23 settings should have retained the state from the previous experiment. Press ‘single capture’. RFSoC Development Kit Getting Started Guide Page 30...
  • Page 31 ’ to increase the attenuation and decrease the signal power entering the PA by 1.65 dB. Press ‘single capture’ to observe the PA now operating in the linear region. This concludes experiment 2. RFSoC Development Kit Getting Started Guide Page 31...
  • Page 32 This introduction to the Avnet Zynq UltraScale+TM RFSoC Development Kit with Qorvo RF Front End has demonstrated usage of the Avnet RFSoC Explorer graphical user-interface to control the ZCU111 development board, generate and acquire signals through the Qorvo RF front-end card in the MATLAB environment.

  • Page 33: Appendix A: Installation Of Usb Uart Driver

    Download and Install the Required Software 1. Using your web browser, navigate to the Silicon Labs website: http://www.silabs.com/products/mcu/pages/usbtouartbridgevcpdrivers.aspx 2. Download the VCP Driver Kit for your PC’s operating system. Drivers for MacOS and Linux are also available. RFSoC Development Kit Getting Started Guide Page 33...
  • Page 34 32-bit (CP210xVCPInstaller_x86.exe) or 64-bit (CP210xVCPInstaller_x64.exe) PC. The installer will guide you through the setup. Accept the license agreement and install the software on your PC. Click Finish button when completed. RFSoC Development Kit Getting Started Guide Page 34...

  • Page 35: Determining The Virtual Com Port

    Follow these instructions to determine the COMx port assigned to the USB-to- UART bridge: 1. Open the Device Manager by right-clicking on , select Properties, then click on the Device Manager. RFSoC Development Kit Getting Started Guide Page 35...
  • Page 36 USB to UART Bridge and its assigned COM port. In the example below, it is COM4. Make note of this COM port number for use with the serial terminal you will use elsewhere in this design tutorial. This concludes these USB UART driver and virtual COM port installation instructions. RFSoC Development Kit Getting Started Guide Page 36...

  • Page 37: Appendix Iii: Getting Support

    Appendix III: Getting Support Avnet Support  If you have any questions about the Avnet Zynq UltraScale+ RFSoC Development Kit, Avnet’s RFSoC Explorer application, or this tutorial please use the UltraScale+ RFSoC Forum on our element14 ZedBoard Community page: https://www.element14.com/zedboardcommunity ...

  • Page 38: Regulatory Compliance Information

    Regulatory Compliance Information RFSoC Development Kit Getting Started Guide Page 38...

  • Page 39: Revision History

    26 Nov, 2019 Revised MATLAB SW Requirements. Revised SD card preparation instruction. Free MATLAB Trial Package for Wireless Communications available here https://www.avnet.com/rfsockit Avnet Qorvo 2x2 Small Cell RF Front-end 1.8GHz Card Hardware User Guide www.avnet.com/rfsockit https://www.xilinx.com/support/documentation/ip_documentation/usp_rf_data_converter/v2_1/pg269-rf- data-converter.pdf https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/rfdc RFSoC Development Kit Getting Started Guide...

This manual is also suitable for:

Zynq ultrascale+ rfsoc zcu111

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