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Related Manuals for Avnet Xilinx Virtex-II
Summary of Contents for Avnet Xilinx Virtex-II
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Page 1: Xilinx Virtex-Ii Development Kit
Xilinx Virtex-II Development Kit Copyright © 2003 Avnet, Inc. AVNET and the AV logo are registered trademarks of Avnet, Inc. All other trademarks are property of their respective owners. Avnet Design Services 1 of 25 Rev 1.0 06/08/2004... -
Page 2: Table Of Contents
DDR SDRAM Test ................................. 25 Example VHDL Project................................25 Copyright © 2003 Avnet, Inc. AVNET and the AV logo are registered trademarks of Avnet, Inc. All other trademarks are property of their respective owners. Avnet Design Services 2 of 25 Rev 1.0... -
Page 3: Figures
Table 13 – Virtex-II Power-up Configuration Modes ..........................24 Table 14 – System ACE Test Designs................................. 24 Copyright © 2003 Avnet, Inc. AVNET and the AV logo are registered trademarks of Avnet, Inc. All other trademarks are property of their respective owners. Avnet Design Services 3 of 25 Rev 1.0... -
Page 4: Introduction
LED test Connector Test DDR SDRAM Memory test Copyright © 2003 Avnet, Inc. AVNET and the AV logo are registered trademarks of Avnet, Inc. All other trademarks are property of their respective owners. Avnet Design Services 4 of 25 Rev 1.0... -
Page 5: Ordering Information
“J2”, should the user wish to program with an alternate method. Copyright © 2003 Avnet, Inc. AVNET and the AV logo are registered trademarks of Avnet, Inc. All other trademarks are property of their respective owners. -
Page 6: Boundary Scan Configuration
Programming pins are provided with J2 as shown in Figure 1. Figure 1 - Fly Wire Connection J2 Copyright © 2003 Avnet, Inc. AVNET and the AV logo are registered trademarks of Avnet, Inc. All other trademarks are property of their respective owners. Avnet Design Services 6 of 25 Rev 1.0... -
Page 7: Configuration Modes
For Boundary Scan mode, place jumpers at JP2 positions 1-2 & 5-6. Copyright © 2003 Avnet, Inc. AVNET and the AV logo are registered trademarks of Avnet, Inc. All other trademarks are property of their respective owners. Avnet Design Services 7 of 25 Rev 1.0... -
Page 8: Jtag Chain
XCCACEMxx_BG388.bsd Table 4 - JTAG Boundary-Scan Description Language (BSDL) files Copyright © 2003 Avnet, Inc. AVNET and the AV logo are registered trademarks of Avnet, Inc. All other trademarks are property of their respective owners. Avnet Design Services 8 of 25 Rev 1.0... -
Page 9: Jumper Settings
+1.5V as Bank1 Vref. Jumper 2-3 assigns half of I/O voltage selected with JP13 as Bank 1 Vref. Copyright © 2003 Avnet, Inc. AVNET and the AV logo are registered trademarks of Avnet, Inc. All other trademarks are property of their respective owners. - Page 10 J102 – 50-pin general purpose System ACE header. J103 – Connector for Power Supply Daughter board. Copyright © 2003 Avnet, Inc. AVNET and the AV logo are registered trademarks of Avnet, Inc. All other trademarks are property of their respective owners. Avnet Design Services 10 of 25 Rev 1.0...
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Page 11: Hardware
Figure 5 - Virtex-II Development Board Block Diagram Figure 6 - Virtex-II Development Board Copyright © 2003 Avnet, Inc. AVNET and the AV logo are registered trademarks of Avnet, Inc. All other trademarks are property of their respective owners. Avnet Design Services 11 of 25 Rev 1.0... -
Page 12: Virtex-Ii Fpga
TX out RX in Table 5 - RS232 Connector Pin-out Copyright © 2003 Avnet, Inc. AVNET and the AV logo are registered trademarks of Avnet, Inc. All other trademarks are property of their respective owners. Avnet Design Services 12 of 25 Rev 1.0... -
Page 13: Led
AMP part number 5-179010-6. When interfacing to other boards care must be taken to tri-state any signals that could interfere with those of the other board. Copyright © 2003 Avnet, Inc. AVNET and the AV logo are registered trademarks of Avnet, Inc. All other trademarks are property of their respective owners. Avnet Design Services 13 of 25 Rev 1.0... -
Page 14: General I/O Interface
GEN_IO2_61 GEN_IO1_63 GEN_IO1_62 GEN_IO2_63 GEN_IO2_62 Copyright © 2003 Avnet, Inc. AVNET and the AV logo are registered trademarks of Avnet, Inc. All other trademarks are property of their respective owners. Avnet Design Services 14 of 25 Rev 1.0 06/08/2004 Released... -
Page 15: Table 8 - General I/O Avbus Connector P2 & P3
TRST# Table 8 – General I/O AvBus Connector P2 & P3 Copyright © 2003 Avnet, Inc. AVNET and the AV logo are registered trademarks of Avnet, Inc. All other trademarks are property of their respective owners. Avnet Design Services 15 of 25 Rev 1.0... -
Page 16: Lvds
* = Optional Driver/Receiver Table 9 – Low Voltage Differential Signaling Pairs (P3) Copyright © 2003 Avnet, Inc. AVNET and the AV logo are registered trademarks of Avnet, Inc. All other trademarks are property of their respective owners. Avnet Design Services 16 of 25 Rev 1.0... -
Page 17: Memory Expansion Connector Interface
MEM_IO_24 +3.3V DATA_AV25 +3.3V MEM_IO_25 Copyright © 2003 Avnet, Inc. AVNET and the AV logo are registered trademarks of Avnet, Inc. All other trademarks are property of their respective owners. Avnet Design Services 17 of 25 Rev 1.0 06/08/2004 Released... -
Page 18: Table 10 - Memory I/O Avbus Connector P4 & P5
MEM_IO_60 Table 10 – Memory I/O AvBus Connector P4 & P5 Copyright © 2003 Avnet, Inc. AVNET and the AV logo are registered trademarks of Avnet, Inc. All other trademarks are property of their respective owners. Avnet Design Services 18 of 25 Rev 1.0... -
Page 19: Auxiliary Connectors(Available Only With Ff1152 Package)
V33_IO_57 V25_IO_59 V25_IO_58 V33_IO_59 V33_IO_58 Copyright © 2003 Avnet, Inc. AVNET and the AV logo are registered trademarks of Avnet, Inc. All other trademarks are property of their respective owners. Avnet Design Services 19 of 25 Rev 1.0 06/08/2004 Released... -
Page 20: Miscellaneous Connectors
For programming the FPGA, a Xilinx parallel/serial connector (Parallel III & MultiLINX) and a JTAG connector (Parallel IV) are provided. Copyright © 2003 Avnet, Inc. AVNET and the AV logo are registered trademarks of Avnet, Inc. All other trademarks are property of their respective owners. Avnet Design Services 20 of 25 Rev 1.0... -
Page 21: Pci/Pcix
AD[46] AD[45] AD[31] AD[30] AD[44] Copyright © 2003 Avnet, Inc. AVNET and the AV logo are registered trademarks of Avnet, Inc. All other trademarks are property of their respective owners. Avnet Design Services 21 of 25 Rev 1.0 06/08/2004 Released... -
Page 22: Table 12 - Pci/Pci-X Connector Pin Assignment And Interface Signals
C/BE[7]# Table 12 – PCI/PCI-X Connector Pin Assignment and Interface Signals Copyright © 2003 Avnet, Inc. AVNET and the AV logo are registered trademarks of Avnet, Inc. All other trademarks are property of their respective owners. Avnet Design Services 22 of 25 Rev 1.0... -
Page 23: Evaluation Boards
“Master-Serial” mode, which will allow the FPGA to be programmed from the System ACE MPM. Copyright © 2003 Avnet, Inc. AVNET and the AV logo are registered trademarks of Avnet, Inc. All other trademarks are property of their respective owners. -
Page 24: Test Designs
“111” Empty Table 14 – System ACE Test Designs Copyright © 2003 Avnet, Inc. AVNET and the AV logo are registered trademarks of Avnet, Inc. All other trademarks are property of their respective owners. Avnet Design Services 24 of 25 Rev 1.0... -
Page 25: On-Board Flash Test
Environment (ISE) development suite. The source code was written in VHDL. See the “readme” file in the “ISE_Project” folder under the “Sample_Code” directory on the CD for more information. Copyright © 2003 Avnet, Inc. AVNET and the AV logo are registered trademarks of Avnet, Inc. All other trademarks are property of their respective owners. Avnet Design Services 25 of 25 Rev 1.0...
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