Table 9 - Cdcm61001 Clock Synthesizer Pin Description; Table 10 - Cdcm61001 Common Application Settings - Avnet Xilinx Zynq 7Z045 Manual

Signal Name
PR[1:0]
OD[2:0]
OS[1:0]
CE
RST_N
XIN
OUT0 P/N
2.4.1.1 CDCM61001 Clock Generation
The CDCM61001 output clocks are generated based on the following formula (assuming
the crystal clock input is 25 MHz):
FOUT = (FIN) (FD) / OD
Equation Variables:
FOUT = Output Frequency
FIN = Clock Input Frequency
FD = Feedback Divider Value
OD = Output Divider Value
Please refer to the CDCM61001 datasheet for detailed tables regarding the Feedback
Divider and Output Divider values. The CDCM61001 FD and OD values are programmed
via dipswitches SW3 and SW4. These dipswitches should be configured prior to powering
up the board.
The following table shows how to set the dipswitches for a common application. All the
values are based on a 25 MHz crystal clock input to the CDCM61001 device.
Interconnect
Technology
SATA
GigE
10 GigE
12 GigE
2.4.1.2 CDCM61001 Programming Mode
The Zynq 7Z045 Mini-Module Plus Development Board allows programming of the PR and
OD values in parallel mode. This is the only mode supported by the device. In parallel
mode, PR and OD values are programmed into the device upon the release of the master
reset signal (rising edge of the MR_N signal). The switches should be set into the correct
position prior to turning on power to the board. Should the switch settings change after
power up the board will have to be power cycled to reset the device.
Direction Pull Up/Pull Down
Input Pull up
Input Pull up
Input Pull up
Input Pull up
Input Pull up
Input Pull up
Input
Table 9 – CDCM61001 Clock Synthesizer Pin Description
OUT0 and
OUT1 (MHZ)
150
125
156.25
187.5
Table 10 – CDCM61001 Common Application Settings
Description
Prescaler and Feedback divider control pins.
Output divider control pins.
Output type select control pins.
Chip enable.
Device reset (active low).
Parallel resonant crystal/LVCMOS input.
Differential output pair.
PR1 PR0
0 0
1 1
1 0
0 1
Page 23
OD2 OD1 OD0
0 1 1
0 1 1
0 1 1
0 0 1