Table of Contents
Advertisement
Quick Links
Advertisement
Table of Contents
Related Manuals for Avnet Xilinx Spartan-3
Summary of Contents for Avnet Xilinx Spartan-3
- Page 1 Xilinx Spartan -3 Development Kit User Guide Copyright © 2003 Avnet, Inc. AVNET and the AV logo are registered trademarks of Avnet, Inc. All other trademarks are property of their respective owners. Avnet Electronics Marketing 1 of 33 Rev 1.0...
-
Page 2: Table Of Contents
Figure 17 - Resistor Jumper Pin-out................................. 25 Figure 18 - Barrel Power Connector "J7"..............................32 Copyright © 2003 Avnet, Inc. AVNET and the AV logo are registered trademarks of Avnet, Inc. All other trademarks are property of their respective owners. Avnet Electronics Marketing 2 of 33 Rev 1.0... - Page 3 Table 27 - AvBus Connector "P2" Pin-out ..............................30 Table 28 - Header "JP1" Pin-out ................................31 Copyright © 2003 Avnet, Inc. AVNET and the AV logo are registered trademarks of Avnet, Inc. All other trademarks are property of their respective owners. Avnet Electronics Marketing 3 of 33 Rev 1.0...
-
Page 4: Introduction
Figure 1 - Spartan-3 Dev (Top Side) Figure 2 - Spartan-3 Dev (Bottom Side) Copyright © 2003 Avnet, Inc. AVNET and the AV logo are registered trademarks of Avnet, Inc. All other trademarks are property of their respective owners. Avnet Electronics Marketing 4 of 33 Rev 1.0... -
Page 5: Demo Applications
Spartan-3 FPGA as the focal point. The block diagram is shown in Figure 4. Copyright © 2003 Avnet, Inc. AVNET and the AV logo are registered trademarks of Avnet, Inc. All other trademarks are property of their respective owners. Avnet Electronics Marketing 5 of 33 Rev 1.0... -
Page 6: Spartan-3 Fpga
FPGA to boundary-scan mode, install shunts on JP2 at locations 1-2 & 5-6 as shown in below. Note that power should be removed when changing Mode select jumpers. Copyright © 2003 Avnet, Inc. AVNET and the AV logo are registered trademarks of Avnet, Inc. All other trademarks are property of their respective owners. Avnet Electronics Marketing 6 of 33 Rev 1.0... -
Page 7: Figure 5 - Boundary Scan Mode Selection Via Jp2
For futher information regarding Xilinx configuration solutions, please visit: http://www.xilinx.com/products/design_resources/config_sol/index.htm Modifying the JTAG Chain Copyright © 2003 Avnet, Inc. AVNET and the AV logo are registered trademarks of Avnet, Inc. All other trademarks are property of their respective owners. Avnet Electronics Marketing 7 of 33 Rev 1.0... -
Page 8: Figure 8 - Jtag Chain Standalone Mode (Default)
FOR FPGA Slave Modes ONLY! Figure 9 – Design Revision “BIT SEL” Jumpers JP3 Copyright © 2003 Avnet, Inc. AVNET and the AV logo are registered trademarks of Avnet, Inc. All other trademarks are property of their respective owners. Avnet Electronics Marketing 8 of 33 Rev 1.0... -
Page 9: Figure 10 - Fly Wire Connection J1
Figure 10 - Fly Wire Connection J1 Copyright © 2003 Avnet, Inc. AVNET and the AV logo are registered trademarks of Avnet, Inc. All other trademarks are property of their respective owners. Avnet Electronics Marketing 9 of 33 Rev 1.0... -
Page 10: Jumper Settings
JP10 “USB EEPROM WC#” – Serial EEPROM write protect, install a shunt to protect programmed data. Default: Open, read/write enabled. Copyright © 2003 Avnet, Inc. AVNET and the AV logo are registered trademarks of Avnet, Inc. All other trademarks are property of their respective owners. Avnet Electronics Marketing 10 of 33 Rev 1.0... -
Page 11: Figure 13 - I/O Voltage Selection Banks 4&5
JP23 “VIDEO CLK DISABLE” – Installing this jumper will disable the 25.175MHz oscillator to the video DAC. Copyright © 2003 Avnet, Inc. AVNET and the AV logo are registered trademarks of Avnet, Inc. All other trademarks are property of their respective owners. - Page 12 The following figure illustrates the default placement of the jumpers installed on the Spartan-3 Development Board. Copyright © 2003 Avnet, Inc. AVNET and the AV logo are registered trademarks of Avnet, Inc. All other trademarks are property of their respective owners.
-
Page 13: Figure 16 - Default Jumper Placement
Copyright © 2003 Avnet, Inc. AVNET and the AV logo are registered trademarks of Avnet, Inc. All other trademarks are property of their respective owners. Avnet Electronics Marketing 13 of 33 Rev 1.0... -
Page 14: Clocks
8-bit option. For detailed information, please see: www.optrex.com/SiteImages/LitCentral/Dmcman_full.pdf Copyright © 2003 Avnet, Inc. AVNET and the AV logo are registered trademarks of Avnet, Inc. All other trademarks are property of their respective owners. Avnet Electronics Marketing 14 of 33 Rev 1.0... -
Page 15: Table 8 - 2X20 Character Lcd Pin-Out
AD14 LCD_EN Table 8 – 2x20 Character LCD Pin-out Copyright © 2003 Avnet, Inc. AVNET and the AV logo are registered trademarks of Avnet, Inc. All other trademarks are property of their respective owners. Avnet Electronics Marketing 15 of 33 Rev 1.0... -
Page 16: Table 9 - Oled Display Pin-Out
An alternative is to simply remove the unused display from the board. The following table illustrates the pins which are common as well as the corresponding pin on the FPGA. Copyright © 2003 Avnet, Inc. AVNET and the AV logo are registered trademarks of Avnet, Inc. All other trademarks are property of their respective owners. Avnet Electronics Marketing 16 of 33 Rev 1.0... -
Page 17: Vga (Db15 & Video Dac)
(1280 X 1024) @ 75Hz requires 135.0MHz. The ADV7125KST140 140MHz device furnished on the board is sufficient for SXGA resolution at 75Hz. Copyright © 2003 Avnet, Inc. AVNET and the AV logo are registered trademarks of Avnet, Inc. All other trademarks are property of their respective owners. Avnet Electronics Marketing 17 of 33 Rev 1.0... -
Page 18: Table 11 - Video Dac - Fpga Pin-Out
2-3 – Power save mode Table 12 – Video DAC Jumpers Copyright © 2003 Avnet, Inc. AVNET and the AV logo are registered trademarks of Avnet, Inc. All other trademarks are property of their respective owners. Avnet Electronics Marketing 18 of 33 Rev 1.0... -
Page 19: Audio Codec
Off – Forces Codec into reset Table 14 – Audio Codec Jumpers Copyright © 2003 Avnet, Inc. AVNET and the AV logo are registered trademarks of Avnet, Inc. All other trademarks are property of their respective owners. Avnet Electronics Marketing 19 of 33 Rev 1.0... -
Page 20: Ps2 Keyboard & Mouse Ports
SWITCH_PB1 SWITCH_PB2 Table 16 - Pushbutton FPGA Pin-out Copyright © 2003 Avnet, Inc. AVNET and the AV logo are registered trademarks of Avnet, Inc. All other trademarks are property of their respective owners. Avnet Electronics Marketing 20 of 33 Rev 1.0... -
Page 21: Leds
LVDS_N13 95.64061 LVDS_P14 95.53837 R132 Copyright © 2003 Avnet, Inc. AVNET and the AV logo are registered trademarks of Avnet, Inc. All other trademarks are property of their respective owners. Avnet Electronics Marketing 21 of 33 Rev 1.0 04/17/2006 Released... -
Page 22: Table 18 - Lvds Fpga Pin-Out
95.18259 AC26 Table 18 - LVDS FPGA Pin-out Copyright © 2003 Avnet, Inc. AVNET and the AV logo are registered trademarks of Avnet, Inc. All other trademarks are property of their respective owners. Avnet Electronics Marketing 22 of 33 Rev 1.0... -
Page 23: Memory
SRAM and Flash devices. See the Software/BSP section of this manual for more information. Copyright © 2003 Avnet, Inc. AVNET and the AV logo are registered trademarks of Avnet, Inc. All other trademarks are property of their respective owners. -
Page 24: Communication (Rs232, 10/100 Ethernet, Usb2.0)
* Note: RTS and CTS are only connected to the FPGA when JP28 and JP29 are in position 1-2. Copyright © 2003 Avnet, Inc. AVNET and the AV logo are registered trademarks of Avnet, Inc. All other trademarks are property of their respective owners. -
Page 25: Figure 17 - Resistor Jumper Pin-Out
IP core from Xilinx. A valid license for this IP may be required to regenerate the project. The following table provides the FPGA pin numbers for the Ethernet PHY interface. Copyright © 2003 Avnet, Inc. AVNET and the AV logo are registered trademarks of Avnet, Inc. All other trademarks are property of their respective owners. Avnet Electronics Marketing 25 of 33 Rev 1.0... -
Page 26: Table 24 - Ethernet Fpga Pin-Out
FX2 modes of operation, see the “EZ-USB FX2 Technical Reference Manual” and the FX2 datasheet available on Cypress Semiconductor’s web site (http://www.cypress.com). Copyright © 2003 Avnet, Inc. AVNET and the AV logo are registered trademarks of Avnet, Inc. All other trademarks are property of their respective owners. Avnet Electronics Marketing 26 of 33 Rev 1.0... -
Page 27: Table 25 - Usb Interface Fpga Pin-Out
Table 25 - USB Interface FPGA Pin-out * Only connected on 3S2000 device. 1500 is a no-connect. Copyright © 2003 Avnet, Inc. AVNET and the AV logo are registered trademarks of Avnet, Inc. All other trademarks are property of their respective owners. Avnet Electronics Marketing 27 of 33 Rev 1.0... -
Page 28: I/O Connectors
The tables on the following pages show pin-outs for the header and AvBus connectors. Copyright © 2003 Avnet, Inc. AVNET and the AV logo are registered trademarks of Avnet, Inc. All other trademarks are property of their respective owners. Avnet Electronics Marketing 28 of 33 Rev 1.0... -
Page 29: Table 26 - Avbus Connector "P1" Pin-Out
AVBUS_TCK JTAG_TRST# Table 26 - AvBus Connector "P1" Pin-out Copyright © 2003 Avnet, Inc. AVNET and the AV logo are registered trademarks of Avnet, Inc. All other trademarks are property of their respective owners. Avnet Electronics Marketing 29 of 33 Rev 1.0... -
Page 30: Table 27 - Avbus Connector "P2" Pin-Out
GEN_IO32 AA26 Table 27 - AvBus Connector "P2" Pin-out Copyright © 2003 Avnet, Inc. AVNET and the AV logo are registered trademarks of Avnet, Inc. All other trademarks are property of their respective owners. Avnet Electronics Marketing 30 of 33 Rev 1.0... -
Page 31: Table 28 - Header "Jp1" Pin-Out
Ground Ground Table 28 - Header "JP1" Pin-out Copyright © 2003 Avnet, Inc. AVNET and the AV logo are registered trademarks of Avnet, Inc. All other trademarks are property of their respective owners. Avnet Electronics Marketing 31 of 33 Rev 1.0... -
Page 32: Power
4.5V – 5.5V, and the ring is ground! Figure 18 - Barrel Power Connector "J7" Copyright © 2003 Avnet, Inc. AVNET and the AV logo are registered trademarks of Avnet, Inc. All other trademarks are property of their respective owners. Avnet Electronics Marketing 32 of 33 Rev 1.0... -
Page 33: Software/Bsp
This “avnet_readme.txt” file discusses the modifications made during the port to the Avnet Spartan-3 Development Board and provides instructions on how to run the demo. Copyright © 2003 Avnet, Inc. AVNET and the AV logo are registered trademarks of Avnet, Inc. All other trademarks are property of their respective owners. Avnet Electronics Marketing 33 of 33 Rev 1.0...
Need help?
Do you have a question about the Xilinx Spartan-3 and is the answer not in the manual?
Questions and answers