Real-Time Clock (Rtc); Power-On Reset; Table 13 - Usb 2.0 Pin Assignments; Table 14 - Rtc Pin Assignments - Avnet Xilinx Zynq 7Z045 Manual

Mini-module plus
Table of Contents

Advertisement

The table below shows the pin assignments of the USB 2.0 PHY to the 7Z045
When operating in host mode, the Zynq Mini-Module must supply 5 V to the endpoint devices.
The Zynq Mini-Module Plus does not have a 5 V power source that is supplied from the
baseboard. To accommodate this requirement the Zynq Mini-Module implements a highly
efficient TI TPS61027 synchronous boost converter. The TPS61027 has the ability to source
up to 1.5A at 3.3 V for the VBUS voltage rail at the USB connector J3.
2.6

Real-Time Clock (RTC)

The Zynq 7Z045 Mini-Module Plus Development Board has a real-time clock circuit that can be
accessed via the I
can count seconds, minutes, hours, days, date, month and year with leap year compensation up to
the year 2100.
The table below show the I
2.7

Power-on Reset

The Zynq 7Z045 Mini-Module Plus Development Board utilizes a power-on reset IC and circuit to insure
the 7Z045 PS_POR# and PS_SRST# signals de-assert in the correct sequence at power-up. To
accomplish this, the Maxim MAX16025TE device is used and is referenced on the board as "U8". As
shipped, the delay sequence is programmed to release the PS_SRST# signal before the PS_POR#
signal. The delay for PS_POR# Is adjustable and set by C66, which as shipped is a 3300pf capacitor.
Please also note that the PS_POR# signal also gates the reset signal of the Ethernet and USB 2.0
PHY devices.
The power-on reset circuit also allows for the reset outputs of the MAX16025TE device to be
controlled manually by way of two push button switches. SW1 when depressed will assert the
PS_POR# signal which will completely reset the processor and all of the 7Z045 PS registers.
Depressing SW2 will assert the PS_SRST# signal which will send a soft reset to the 7Z045 PS
block. This reset signal will reset the processor but retain register data.
Both reset outputs can be asserted low together by placing a jumper on JP6 which is a master
reset for the MAX16025TE device.
Net Name
7Z045 Pin #
USB_D0
K17
USB_D1
G22
USB_D2
K18
USB_D3
G21
USB_D4
L17
USB_D5
B21
Table 13 – USB 2.0 Pin Assignments
2
C interface. The Maxim DS1337 device is used for this purpose. The DS1337
2
C signals and their connection to the 7Z045.
Net Name
2
I
C_SDA
2
I
C_SCL
Table 14 – RTC Pin Assignments
Net Name
USB_D6
USB_D7
USB_STP
USB_NXT
USB_DIR
USB_CLK
USB_RESET#
7Z045 PIN #
F19
A19
Page 26
7Z045 Pin #
A20
F18
L18
H21
H22
H17
A18 or SW2

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the Xilinx Zynq 7Z045 and is the answer not in the manual?

Subscribe to Our Youtube Channel

Table of Contents