Gtx For Fmc Expansion Connector, Sfp, Display Port And Sma (Baseboard); Table 4 - Gtx Pin Assignments For Pci Express - Avnet Xilinx Zynq 7Z045 Manual

The PCI Express transmit lanes are AC coupled (DC blocking capacitors are included in the
signal path) on the baseboard as required by the PCI Express specification.
Bank 112 GTX Instance
GTX_X0Y15
(PCIE LANE 0)
GTX_X0Y14
(PCIE LANE 1)
GTX_X0Y13
(PCIE LANE 2)
GTX_X0Y12
(PCIE LANE 3)
PERST#
2.2.2.1 PCI Express Configuration Timing
The Zynq 7Z045 Mini-Module Plus Development Board meets the 200 ms configuration
time requirement for ATX based PC systems when configuring from the QSPI interface.
2.2.3

GTX for FMC Expansion Connector, SFP, Display Port and SMA (Baseboard)

Four other high-speed gigabit interfaces from the Mini-Module Plus Baseboard 2 are connected
to the 7Z045 via the JX1 connector. Each interface is one lane wide and all reside on bank 109
of the 7Z045.
One GTX transceiver port is connected to the baseboard's FMC LPC connector. The FMC
LPC connector has one gigabit lane dedicated to it for use with FMC daughter cards.
One GTX transceiver port is connected to the baseboard's SFP interface.
One GTX transceiver port is connected to the baseboard's SMA interface.
One GTX transceiver port is connected to the baseboard's Display Port interface (TX only).
Net Name
JX2_MGTTX2_P
JX2_MGTTX2_N
JX2_MGTRX2_P
JX2_MGTRX2_N
JX2_MGTTX3_P
JX2_MGTTX3_N
JX2_MGTRX3_P
JX2_MGTRX3_N
JX2_MGTTX0_P
JX2_MGTTX0_N
JX2_MGTRX0_P
JX2_MGTRX0_N
JX2_MGTTX1_P
JX2_MGTTX1_N
JX2_MGTRX1_P
JX2_MGTRX1_N
JX1_SE_IO_32
Table 4 – GTX Pin Assignments for PCI Express
Page 14
7Z045 Pin #
N4
N3
P6
P5
P2
P1
T6
T5
R4
R3
U4
U3
T2
T1
V6
V5
AC14