Xilinx Zynq 7Z045 Ap Soc; Gtx Interface; Table 2 - Zynq 7Z045 Ap Soc Features - Avnet Xilinx Zynq 7Z045 Manual

2.1

Xilinx Zynq 7Z045 AP SoC

The Zynq 7Z045 AP SoC device available in the FFG900 package has an impressive list of
features. The device is made up of two main systems one of which is the Processing System (PS)
and the other Programmable Logic (PL). The table below lists some of the 7Z045 features.
Processing System
Processor Core
Processor Extensions
Max Frequency
L1 cache
L2 cache
On-Chip Memory
External Memory Controllers
External Static Memory Controllers
DMA Channels
Peripherals
Security
Programmable Logic
Programmable Logic Cells
LUTs
Flip-Flops
Block RAM
DSP Slices
PCI Express (Root Complex or Endpoint)
Analog Mixed Signal
Security
2.2

GTX Interface

The GTX transceiver is a full-duplex serial transceiver for point-to-point transmission applications.
Up to 16 transceivers are available on a single 7Z045 FFG900 device. The transceiver block is
designed to operate at up to 12.5 Gb/s per channel, including the specific bit rates used by the
communications standards listed in the following table. Only the -3 speed grade part is capable of
12.5 Gb/s. The -1 speed grade part is capable of 8.0 Gb/s in the FF package.
The Zynq 7Z045 GTX transceivers are grouped into four transceivers per bank. Banks 109, 110,
111, and 112 are the GTX banks. Each GTX bank has two inputs for reference clocks. The Zynq
Mini-Module Plus Development Board only uses Bank 109 and 112. GTX banks 110 and 11 are
left unconnected.
When mated with a Mini-Module Plus Baseboard 2, bank 112 interfaces to a PCI Express x4
connector while Bank 109 interfaces to a FMC serial gigabit lane, and SFP module, a Display Port
connector (TX Only), and one lane of SMA connectors.
Dual ARM Cortex-A9 MPCore
NEON and Single/Double Precision Floating Point for each processor
667 MHz (-1)
32 KB Instruction, 32 KB Data per processor
512 KB
256 KB
DDR3, DDR3L, DDR2, LPDDR2
2X Quad SPI, NAND, NOR
8 (4 dedicated to PL)
2x UART, 2x CAN, 2x SPI, 2x I
RSA, AES, SHA 256b
350 K
218,600
437,200
2,180 KB
900
Gen2 x8
2x 12-bit, MSPS ADCs with up to 17 differential inputs
AES, SHA 256b
Table 2 – Zynq 7Z045 AP SoC Features
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C, 4x 32b GPIO