Communication; 10/100/1000 Ethernet Phy; Figure 10 - 10/100/1000 Ethernet Interface - Avnet Xilinx Zynq 7Z045 Manual

2.5

Communication

The Zynq 7Z045 Mini-Module Plus Development Board utilizes Ethernet, USB 2.0 (Host mode or
Endpoint) and USB UART physical layer transceivers for communication purposes. Network
access is provided by a single 10/100/1000 Mb/s Ethernet PHY device, which is connected to
7Z045 via a standard RGMII interface. The PHY device connects to the outside world with a
standard RJ45 connector.
Serial port communication to the embedded ARM processor or ZYNQ PL fabric is provided through
a Cypress USB-RS232 transceiver.
2.5.1

10/100/1000 Ethernet PHY

The PHY device is a Marvel 88E1518. The PHY is connected to a Tyco Electronics RJ-45 jack
with integrated magnetics (part number: 1840808-7. The jack also integrates two LEDs that
indicate a valid link and traffic over the interface. The PHY clock is generated from a 25 MHz
crystal. The following figure shows a high-level block diagram of the interface to the Ethernet PHY.
The PHY has two methods that can be used to reset the device. The PHY reset signal is ORed
(active low) with the on-board power-on reset circuit and one of the I/O pins in bank 500. If
having the 7Z045 reset the device is desired toggle pin B24 LOW. To manually reset the PHY
SW1 can be pressed. See section 2.7 for details about the power-on reset circuit.
Figure 10 – 10/100/1000 Ethernet Interface
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