Cdcm61001 Programmable Lvds Clock Synthesizer; Figure 9 - Cdcm61001 Clock Synthesizer - Avnet Xilinx Zynq 7Z045 Manual

The on-board 200 MHz LVDS oscillator provides the system clock input to the global clock tree.
This 200 MHz clock can be used in conjunction with the 7Z045's internal clock generators to
generate the various logic clocks and the clocks forwarded to the DDR3 SDRAM devices.
Additionally, there is an on-board 33 MHz LVTTL clock source connected to bank 500 and serves
as the PS system clock.
2.4.1

CDCM61001 Programmable LVDS Clock Synthesizer

The Zynq 7Z045 Mini-Module Plus Development Board design uses the TI CDCM61001 LVDS
frequency synthesizer for generating various clock frequencies as an input reference clock for
GTX bank 109. A list of features included in the CDCM61001 device is shown below.
–
Output frequency range: 43.75 MHz to 683.264 MHz
–
RMS period jitter: 0.509 ps @ 625 MHz
–
Output rise and fall time: 255 ps (maximum)
–
Output duty cycle: varies dependent on output frequency
The following figure shows a high-level block diagram of the CDCM61001 programmable clock
synthesizer. Inputs OS0 and OS1 are hard wired to use the LVDS mode of the CDCM61001 device.
Figure 9 – CDCM61001 Clock Synthesizer
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