Nokia Mobile Phones NSE-5 Series Service Manual page 68

NSE–5
System Module
Frequency Synthesizers
Both the UHF- and the VHF-VCO are locked with PLLs to a stable
frequency source, which is a VCTCXO-module (Voltage Controlled
Temperature Compensated Crystal Oscillator). The VCTCXO is running at
13 MHz and is locked to the frequency of the base station by means of an
AFC (Automatic Frequency Control).
The UHF PLL is common for both systems and is located in the SUMMA
except for an external UHF–VCO. The part in the SUMMA includes a
64/65 (P/P+1) prescaler, a N- and A-divider, a reference divider, a phase
detector and a charge pump for the external loop filter. The UHF–VCO is
running at 2 GHz. The UHF local oscillator signal is generated by first
dividing the UHF-VCO signal by two in the CRFU3 prescaler. After that the
signal is fed to the SUMMA prescaler. The latter prescaler is a dual
modulus divider. The output of the prescaler is fed to N- and A-divider,
which produce the input to the phase detector. The phase detector
compares this signal to the reference signal, which is derived by dividing
the output from the VCTCXO.
The output of the phase detector is connected to the charge pump, which
charges or discharges the integrator capacitor in the loop filter in
accordance with the phase difference between the measured frequency
and the reference frequency. The loop filter serves to filter the voltage
across the integrator capacitor and generates a DC voltage that controls
the frequency of UHF-VCO. The loop filter defines the step response of
the PLL (settling time) and effects the stability of the loop. To preserve the
stability of the loop a resistor is included for phase compensation. Other
filter components are for sideband rejection.
The dividers are controlled via the serial bus. SDATA is for data, SCLK is
the serial clock for the bus and SENA1 is a latch enable, which enables
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Figure 16. Frequency Synthesisers
PAMS
Technical Documentation
LO to GSM1800
LO to GSM900
Issue 1 07/99