Nokia Mobile Phones NSE-5 Series Service Manual page 50

NSE–5
System Module
The MAD2PR1 operates from a 13 MHz system clock, which is generated
from the 13Mhz VCXO frequency. The MAD2PR1 supplies a 6,5MHz or a
13MHz internal clock for the MCU and system logic blocks and a 13MHz
clock for the DSP, where it is multiplied to TBD MHz DSP clock. The
system clock can be stopped for a system sleep mode by disabling the
VCXO supply power from the CCONT regulator output. The CCONT
provides a 32kHz sleep clock for internal use and to the MAD2PR1, which
is used for the sleep mode timing. The sleep clock is active when there is
a battery voltage available i.e. always when the battery is connected.
MAD2PR1 pinout
MAD2PR1 pins and their usage are described in the following table.
Pad Pad Name
No
1 MCUGenIO0
2fp Col0
3 LEADGND0
4 Col1
5 Col2
6 Col3
7 Col4
8 LCDCSX
9 GND0
10 Row5LCDCD
11 Row4
12 LEADVCC0
13 Row3
14 Row2
15 Row1
16fp Row0
17fp (JTDO)
18 VCCSYS0
19fp (JTRst)
20fp (JTClk)
21 VCCIO0
Page 2 – 36
– FLEXPOOL (DAS00308 FlexPool Specification)
– SERRFI (DAS00348 COBBA_GJP Specifications)
Table 10. MAD2PR1 pin list
Direction Drive +
pull
IO
IO 2 down
PWR
IO
IO
IO
IO
IO
PWR
IO 2 up
IO 2 up
PWR
IO 2 up
IO 2 up
IO 2 up
IO 2 up
IO 2 up
PWR
IO 2 down
IO 2 up
PWR
Technical Documentation
Explanation
2 BattIO
keypad matrix
digital gnd
2 keypad matrix
2 keypad matrix
2 keypad matrix
2 no connection
2 seriel LCD chip select
digital gnd
Seriel LCD command/data
and row5
keypad matrix
V_core
keypad matrix
keypad matrix
keypad matrix
keypad matrix (+powerkey)
flex pool
V_core
flex pool
flex pool
Vbb
PAMS
macro
functions
x205 ee-
prom ser-
iel data
sda
key
gnd
key
key
key
Vol up
gnd
JTDO de-
fault on
JTRst
JTClk
Issue 1 07/99