Nortel Communication Server 1000 Manual page 105

Automatic clock switching
If the EREF command is selected in LD 60, tracking on the primary or
secondary reference clock is automatically switched in the following
manner:
•
If software is unable to track on the assigned primary reference clock, it
switches to the secondary reference clock and sends appropriate DTC
maintenance messages.
•
If software is unable to track on the assigned secondary reference
clock, it switches to free run.
Clock configurations
Clock Controllers can be used in a single or a dual CPU system.
A single CPU system has one Clock Controller card. This card can
receive reference clocks from two sources referred to as the primary and
secondary sources. These two sources can originate from a PRI2, DTI2,
etc. PRI2 cards such as the NT8D72BA are capable of supplying two
references of the same clock source. These are known as Ref1 (available
at J1) and Ref2 (available at J2) on the NT8D72BA.
The NT5D97AD card is capable of supplying two references from each
clock source, that is, four references in total. NT5D97AD can supply Clk0
and Clk1 from Unit 0 and Clk0 and Clk1 from Unit 1. Either Unit 0 or Unit
1 can originate primary source, as shown in
Option 1" (page 108)
111).
There is one Clock Controller cable required for the DDP2 card, which
is available in four sizes; this is the NTCG03AA/AB/AC/AD. Refer to
"Reference clock cables" (page 99)
Table 48 "Clock Controller options - summary" (page 105)
clocking options. Table 49 "Clock Controller options - description" (page
106) explains the options in more detail.
Table 48
Clock Controller options - summary
CC Option
Option 1
Option 2
Nortel Communication Server 1000
DASS2 Fundamentals
NN43001-571 04.01 4 June 2010
Copyright © 2007-2010 Nortel Networks. All Rights Reserved.
NT5D97AD Dual-port DTI2/PRI2 card 105
through Figure 30 "Clock Controller Option 4" (page
for more information.
CPU Type
Single
Dual
Figure 27 "Clock Controller
summarizes the
Notes
Ref from P0 on Clk0
Ref from P1 on Clk0
Ref from P0 on Clk0
Ref from P0 on Clk1