Kit Operation
This arrangement allows the ADS1271EVM to be stacked with other ADS1271EVMs in either mode, as
long as all boards in the stack are in the same mode.
A motherboard can sense which state the switch is in and configure itself appropriately by monitoring the
FSDIR pin on J2. This pin is high when FSOUT is active and FSR is an input, and low when FSOUT is
disconnected and FSR is an output (that is, it carries the DRDY signal).
5.4
Clock Source
5.4.1
Onboard Oscillator
The ADS1271 requires a clock. A 25MHz clock oscillator is provided on the EVM, and is selected as the
clock source for the device when OBCLKSEL (J2.19) is high.
5.4.2
External Oscillator
When OBCLKSEL (J2.19) is low, the clock source for the ADS1271 is provided from J2.17, and the
on-board clock oscillator is shut down.
6
Kit Operation
The following section provides informationon using the ADS1271EVM-PDK, including setup, program
installation, and program usage.
8
ADS1271EVM & ADS1271EVM-PDK
www.ti.com
SBAU107 – November 2004
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