Texas Instruments ADS1271EVM User Manual page 7

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5.1.1 Buffer Amplifiers
The buffer amplifiers on this EVM are OPA1632s (U5, U6). These amplifiers are optimized for AC
performance and are configured as fully-differential unity gain buffers. They require ±15V supplies, which
are provided from J3 pins 1 and 2.
The OPA1632 requires a common mode voltage, which is provided on this EVM by U2 and U3. Some
users may not wish to use the buffer amplifier section and provide the ±15V supplies. If the ±15V supplies
are not connected, then having a voltage on the V
ratings. Thus, U2 and U3 provide a separate 2.5V reference for the buffer amplifier section rather than
using the same reference as the ADS1271, which would always be powered. For this reason, U2 and U3
power is provided through a separate regulator, U11.
5.2 Digital Control
The digital control signals can be applied directly to J2. The modular ADS1271EVM can also be
connected directly to a DSP or microcontroller interface board, such as the HPA449. For a current list of
compatible interface and/or accessory boards for the EVM or the ADS1271, see the relevant product
folder on the TI web site.
5.3 Communication Modes
The ADS1271EVM has a digital routing network which can help simulate several possible system
connections. The routing network also provides level-shifting, which allows the ADS1271 to be operated at
any supported logic level regardless of the logic level used on J2. Note that you are not required to include
this circuitry in your own designs; typically no glue logic is required to connect one or more ADS1271s to a
processor.
5.3.1 Routing control
Routing is controlled by pins CLKRMODE, CLKXMODE, and OBCLKSEL on J2. CLKRMODE controls the
direction and connection of CLKR. When CLKRMODE is low, CLKR is an input connected only to SCLK.
When CLKRMODE is high, CLKR becomes an output connected to SCLK, and SCLK is tied to CLK. This
connection can be useful in both FSYNC and SPI modes. A pulldown on CLKRMODE makes FSYNC
mode the default setting.
When CLKXMODE is high, CLKX is an output connected to CLK. This setting is primarily useful for certain
configurations using TI's McBSP, where CLKX can be used as a reference clock input for the serial port.
When CLKXMODE is low, CLKX on J2 is unconnected. A pulldown on CLKXMODE makes this
configuration the default.
OBCLKSEL selects between one of two master clock sources. When OBCLKSEL is high, the on-board
clock is active and used for the master clock. When OBCLKSEL is low, the master clock is taken from
EXTCLK on J2, and the on-board oscillator is disabled. A pulldown on OBCLKSEL makes this setting the
default.
5.3.2 Using the ADS1271 communication modes
You can use either of the two ADS1271 interface modes with the ADS1271EVM. The interface modes are
chosen manually using switch S7, and cannot be selected electrically.
The FSR and FSOUT pins on J2 operate differently depending on the communication mode. In SPI mode,
FSR, which is on the socket on the bottom side of the board, carries the DRDY output signal from the first
ADC (U8), the second ADC (U7) DRDY line is not connected, and the FSOUT pin on the header on the
top side of the board is not connected. In FSYNC mode, the FSYNC pins of both ADCs are tied together,
and the signal on FSR is copied to the top connector on pin FSOUT.
SBAU107 – November 2004
pins of the amplifiers would exceed their maximum
OCM
ADS1271EVM & ADS1271EVM-PDK
EVM Operation
7