Texas Instruments ADS1271EVM User Manual page 4

Power Supplies
Pin Number Signal
J2.1 SYNC
J2.2 MODE0
J2.3 CLKX
J2.4 DGND
J2.5 SCLK
J2.6 MODE1
J2.7 Unused.
J2.8 FSDIR
J2.9 Top: FSOUT
Bottom: FSR
J2.10 DGND
J2.11 Unused
J2.12 CLKRMODE
J2.13 Top: DIN
Bottom: DOUT
J2.14 CLKXMODE
J2.15 Unused
J2.16 SCL
J2.17 EXTCLK
J2.18 DGND
J2.19 OBCLKSEL
J2.20 SDA
4 Power Supplies
J3 provides connection to the common power bus for the ADS1271EVM. Power is supplied on the pins
listed in Table 5.
Signal
+AVDD: +15V to power buffer amplifier section
+5VA
DGND
+1.8VD
+3.3VD
4 ADS1271EVM & ADS1271EVM-PDK
Table 4. Digital Interface Pinout (J2)
Description
Synchronization Control
0 = High-Speed Mode
1 = Low-Power Mode
(In either case, only if Mode1=1)
CLKXMODE = 1: master clock output
CLKXMODE = 0: no connection
Digital ground
Serial Clock
0 = High-Resolution Mode
1 = Mode determined by MODE0
Indicates FSR direction:
0 = Output (DRDY in SPI mode)
1 = Input (FSYNC mode)
FSOUT: in FSYNC mode, copy of FSR; in SPI mode, not connected
FSR: in FSYNC mode, frame-sync input; in SPI mode, DRDY output from U8
Digital ground
0 = Use CLKR for SPI Clock
1 = Use ADC Clock for SPI clock
Top: Serial data input
Bottom: Serial data output
0 = CLKX is High Z
1 = CLKX outputs ADC master clock
2
I C bus serial clock
External ADC clock input
Digital ground
Onboard Clock Select:
High to select onboard clock instead of external clock.
2
I C bus data line
Table 5. Power Supply Pinout
Pin Number
1 2
3 4
5 6
7 8
9 10
Signal
–AVDD: –15V to power buffer amplifier section
Unused
AGND
Unused
+5VD
SBAU107 – November 2004
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