Xilinx FMC XM101 LVDS QSE User Manual page 19

PCA9543 Device Select Code as well as specific Device Code Select address when the
XM101 is connected to a Xilinx board as defined in
Table 1-8: PCA9543 IIC Switch Device Select Code
Bit 7:4 Device
Type Identifier
The PCA9543 has a Control register which must be initialized by the IIC bus master to
enable the channel 0 downstream IIC port. Channel 0 must be enabled prior to attempting
to communicate with the two downstream programmable clock devices on the XM101.
After the IIC bus master enables PCA9543 channel 0 downstream IIC bus, the bus master
can communicate directly with either Si570 component without further interaction with
the Control register. The Control Register can be read by the IIC bus master. Table 11
defines the PCA9543 Control Register.
Table 1-9: PCA9543 Control Register
Notes:
1. Channel 1 must be set to a logic 1 state by IIC bus master prior to attempting to
2. Channel 0 must be set to a logic 1 state by IIC bus master prior to attempting to
The two downstream IIC devices connected to the PCA9543 are at the same IIC address:
•
•
The U4 PCA9543 IIC bus switch to J1 FMC HPC connections are shown in
Table 1-10: IIC Bus Switch to J1 FMC HPC Connections
FMC XM101 User Guide
UG538 (v1.1) September 24, 2010
Bit 3 Bit 2
1110 0 GA0
Bit 7:4 Bit 3:2
XXXX XX
communicate with the Si570 U2.
communicate with the Si570 U1.
Si570 U1 IIC address is at 0x5D, PCA9543 control register bits CR[1:0] = 01
Si570 U2 IIC address is at 0x5D, PCA9543 control register bits CR[1:0] = 10
U4 PCA9543 IIC Bus Switch
Net Name Pin Number
SDA U4.13
SCL U4.12
www.xilinx.com
XM101 Board Technical Description
Table 1-1, page
Bit 0
Bit 1
LSB
Connected to mezzanine FMC
GA1 Read/Write
HPC interface
Bit 1
Channel 1
(1)
Enable
J1 FMC
Connector
Pin Number
C31
C30
7.
Description
Bit 0
Channel 0
(2)
Enable
Table 1-10.
19