Xilinx FMC XM101 LVDS QSE User Manual page 14

Chapter 1: XM101
The P1–P4 QSE to J1 FMC HPC connectivity is show in
page
Table 1-3: P1 QSE0 to J1 FMC HPC Connections
P1 Odd Side
Pin
Net Name
Number
LA02_P 1
LA02_N 3
LA04_P 7
LA04_N 9
LA06_P 13
LA06_N 15
LA08_P 19
LA08_N 21
LA00_CC_P 25
LA00_CC_N 27
LA10_P 31
LA10_N 33
LA12_P 37
LA12_N 39
LA14_P 41
LA14_N 43
LA16_P 47
LA16_N 49
14
17.
J1 FMC
Connector
Pin Pin
Name Number
A1 H7
A2 H8
C1 H10
C2 H11
E1 C10
E2 C11
G1 G12
G2 G13
I1 G6
I2 G7
K1 C14
K2 C15
M1 G15
M2 G16
O1 C18
O2 C19
Q1 G18
Q2 G19
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Table 1-3
P1 Even Side
Pin
Net Name
Number
LA03_P 2
LA03_N 4
LA05_P 8
LA05_N 10
LA07_P 14
LA07_N 16
LA09_P 20
LA09_N 22
LA01_CC_P 26
LA01_CC_N 28
LA11_P 32
LA11_N 34
LA13_P 38
LA13_N 40
LA15_P 42
LA15_N 44
UG538 (v1.1) September 24, 2010
through Table 1-6,
J1 FMC
Connector
Pin Pin
Name Number
B1 G9
B2 G10
D1 D11
D2 D12
F1 H13
F2 H14
H1 D14
H2 D15
J1 D8
J2 D9
L1 H16
L2 H17
N1 D17
N2 D18
P1 H19
P2 H20
FMC XM101 User Guide