Rastergraf
1.2 Functional Description
As an aid to understanding the VFX-M, a block diagram is provided at the
end of this section. The feature set of the VFX-M includes:
• 128-bit 50 MHz Number Nine Graphics Controller
• Embedded VGA controller and BIOS
• 2 Kb serial EEPROM
• 128 KB Flash PROM
• 64 MB Pixmap memory
• Better than 1600 x 1280 displayable analog resolution
• 8-bit overlay (when running 16 or 32 bpp display)
• 8 MB high speed VRAM supports multiple display pages
• 2 MB high speed DRAM supports bit-mapped mask buffer
• Hardware pan, zoom, and scroll and bitmapped cursors
• PLL controlled pixel and memory clocks
• Non-interlaced, interlaced, and high refresh rate displays
• Three status LEDs (controlled by host software)
• Single 25-pin Cannon Micro D-Sub supplies RGB and Serial I/O
• PMC single-wide module
• Ruggedized version (contact Rastergraf for availability)
• OpenGL Library
• Graphics Subroutine Package
• X11R6 X Window System Server with GLX (OpenGL extensions)
• X Windows and Windows NT build options
The Imagine 128 Series 2 (I128S2) is a 128-bit graphics controller with
accelerated 2D and 3D patterned lines and shaded triangles, Z buffer, and
3D volume clipping. It provides a high performance PCI 2.1 compliant
interface with no additional external logic required.
The I128S2 is implemented using a Symmetric Multi-Graphic Processor
(SMGP) architecture. This architecture allows the execution of two
drawing commands simultaneously with totally independent parameters.
The Drawing Engine commands provide all of the normally required
operations including: BitBLT, Line, Triangle, Write Image, and Read
Image. Software may interact with the I128S2 by directly manipulating
pixels through the Memory Windows interface. A secondary Copy
Engine can be used to independently move pixmaps from one memory
area to another.
The I128S2 is implemented in a 0.5 micron 3.3 volt CMOS gate array
process and is packaged in a 352 PBGA, (Plastic Ball Grid Array).
Key I128S2 Device Features:
1-2 General Information
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