Table 4-1 Mclk And Vclk Frequency Selections - Rastergraf VFX-M User Manual

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Table 4-1 MCLK and VCLK Frequency Selections

FS1 FS0
0
0
1
1
Notes: MPLL and VPLL are the frequencies resulting from parameters
programmed into the TVP3030's Memory and Video PLL clock
synthesizers.
FS1 is programmed via the VFX-M Auxiliary Control Register.
FS0 is programmed via the I128S2 VGA Core (see previous page)
A consequence of the dual clock nature of the I128S2 is that if you read a
register driven by the pixel clock (e.g. VCOUNT), you may get erratic
results. You have to read the comparison flag or use interrupts to get
correct results. The reason for this is simple: the VCOUNT register can
change state in the middle of an I128S2 read cycle. Its operations are
totally asynchronous to the I128S2 PCI bus interface clock.
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DECLK MCLK
0 40 MHz 50.11 MHz
1 40 MHz 50.11 MHz
0 50 MHz MPLL
1 50 MHz MPLL
VCLK
25.057 MHz
28.636 MHz
VPLL
VPLL
Troubleshooting 4-9