Pix Bus; Dd Bus; Mbd Bus; I128S2 Vga Support - Rastergraf VFX-M User Manual

Rastergraf
functions (video clock synchronous). The I128S2 has inputs for the
VRAM shift and load clocks so that it can keep track of blanking.
There are three secondary buses on the I128S2: the 128-bit PIX bus, the
32-bit DD bus, and the 16-bit MBD bus.

PIX Bus

The 128-bit PIX memory data bus is connected directly to the Video
RAM (VRAM) and pixmap display memory (DRAM). The VFX-M can
have a maximum of 8 MB of VRAM display memory and 64 MB of
DRAM.

DD Bus

As shown in the Block Diagram, the VRAM output shift registers are
ordinarily the source display data and drive the RAMDAC. However, in
order to support the display features of VGA, display data has to be passed
through the I128S2's VGA core first: pixel data is read a raster line at a
time from the VRAM (over the PIX bus) and piped through an internal
FIFO to the core. The low 8 bits of the DD bus provide the VGA pixel
data from the core to the RAMDAC's special VGA port. This is sufficient
for 640 x 480 displays. The TVP3030 PLLs come up in a default VGA
mode, so they don't need to be set up. The DD bus is also utilized in a
design which has DRAM for display memory. The VFX-M doesn't make
use of this feature.

MBD Bus

The MBD bus serves as a separate "private" data bus for the RAMDAC,
VFX-M control register, and Mask Buffer RAM, and there are two
address spaces for this bus: one for the Mask Buffer RAM, the other for
the RAMDAC. The M4LV-128/64 PLD controls access to the RAMDAC
address space, and allows it to be shared among the RAMDAC and VFX-
M control register.

4.2.6 I128S2 VGA Support

The VGA core is only used to provide basic PC compatibility, and is a
device unto itself, independent of the primary CRT Controller section.
From an external standpoint, it shares the memory and CRT control lines
with the CRT Controller and Memory Controller. The VGA Core is
described at some length in the I128S2 Technical Manual.
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Troubleshooting 4-7