Rastergraf
4.4 TVP3030 RAMDAC
The following information is derived from the Texas Instruments
TVP3030 data sheet. You can obtain the complete data sheet from the TI
web page:
The TVP3030 is an advanced Random Access Memory Digital to Analog
Converter (RAMDAC). The TVP3030 has a 128-bit wide video input
port, enabling 24-bpp displays at resolutions up to 1600 x 1280 at a 76-Hz
refresh rate. 24-bpp graphics at 1280 x 1024 resolution may be
implemented at even higher refresh rates. A 128-bit wide pixel bus
provides a 4:1 24 bpp mode (128-bit bus width for overlay and RGB). The
byte router function allows pseudo-color or monochrome image data to be
taken from the red, green, or blue color channels. This enables high
performance 24-bpp architectures organized as red, green, and blue
memory banks to provide 8-bpp modes as well.
The TVP3030 supports many pixel formats. Data can be split into 4 or 8
bit planes for pseudo-color mode or split into 12-, 16- or 24-bit true-color
and direct-color modes. For the 24-bit direct color modes, an 8-bit overlay
plane is available. The 16-bit direct- and true-color modes can be
configured to IBM XGA [565], TARGA [5551], or [664] as another
existing format. An additional 12-bit mode [4444] is supported with 4 bits
for each color and overlay. All color modes support selection of little or
big endian data format for the pixel bus. The TVP3030 is software
compatible with the TVP3026 and Bt476/8 color palettes.
Note that while the TVP3030 also supports 24 bpp packed modes, the
I128S2's accelerated functions do not. Nevertheless, Rastergraf's GLP
software will operate correctly, but uses the I128S2 only in "dumb
framebuffer" mode.
Two fully programmable PLLs for pixel clock and memory clock
functions are provided for dramatic improvements in graphics system cost
and integration. A third loop clock PLL is incorporated making pixel data
latch timing much simpler than with other existing color palettes. In
addition, an external digital clock input is provided for VGA modes. The
reference clock output is driven by the loop clock PLL and provides a
timing reference to the graphics accelerator. The shift clock output may be
used directly as the VRAM shift clock.
The TVP3030 also integrates a complete, IBM XGA-compatible hardware
cursor on chip, making significant graphics performance enhancements
possible. Additionally, color-keyed switching is provided, giving the user
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