Flash Eeprom; Table 4-9 Flash Eeprom Logical/Physical Address Mapping - Rastergraf VFX-M User Manual

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4.7 Flash EEPROM

The VFX-M has a location for installing a 128 KB Flash EEPROM.
The code in the PROM cannot be directly executed. It must be read by the
host CPU into its memory and executed from there. The I128S2 accesses
the PROM data through the Mask Buffer data port, which is also used to
access the RAMDAC and Auxiliary Control Registers.
The multiplexed Mask Buffer DRAM address bits contain both the high
and low order address lines for the PROM. The high order lines appear
first and so must be latched externally. In the table below, LMA refers to
latched addresses, MAD refers to the low order lines which don't have to
be latched.
Although in most cases the standard BIOS PROM would be 64 KB, a 128
KB is used on the VFX-M due to a bug in the I128S2 which requires that
the minimum PROM size be 128 KB.
The VFX-M has overlapping positions to accommodate 32, 40 and 48 pin
devices. Since the address connections on all three devices don't match
exactly, to simplify the layout some of the address lines have been
redefined:

Table 4-9 Flash EEPROM Logical/Physical Address Mapping

PROM 16 15 14
Logical 16 11 10
Physical 10 17 13
(LMA)
Physical -- -- --
(MAD)
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13 12 11 10 9
9 8 15 14 13
12 -- 15 11 14
-- 8 -- -- --
8 7 6 5 4 3
12 7 6 5 4 3
16 - - - - -
-- 7 6 5 4 3
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2 1 0
2 1 0
- - -
2 1 0