Pci Bus Interface; Video Ram (Vram) - Rastergraf VFX-M User Manual

Rastergraf

4.2.1 PCI Bus Interface

Although the actual PC boards are radically different, the standard PCI
bus board and the VFX-M are virtually identical when it comes to the
electrical side of things. The Number Nine I128S2 serves not only as the
graphics controller but also as the PCI bus interface.
The VFX-M uses the I128S2 to provide the PCI 2.1 32-bit 33 MHz
compliant bus interface. PCI signals connect to the I128S2 only. The
placement and routing is done to the PCI specifications, keeping the trace
lengths to 1.5" for bus signals and 2.5" for the clock.
In addition to providing the actual 32-bit data path between PCI bus and
the I128S2 internal registers and 128-bit wide memory path, the I128S2
performs the PCI/local address mapping and decoding. It has on-chip
FIFOs for buffering data.
The I128S2 has decodes for: PCI Configuration Registers, Copy and
Drawing Engine Registers, one XY and two Linear Memory Windows for
accessing VRAM and DRAM, Flash PROM Window, I/O Register
Window, and a VGA Core register set. Except for the PCI Configuration
Registers, which have a fixed size and address, each decode has a Base
Address Register (BAR) associated with it.
The I128S2 also provides mapping for the Mask Buffer DRAM and the
RAMDAC. Since the VFX-M has a configuration EEPROM and three
diagnostic LEDs, the RAMDAC address space is partitioned into
subsections to allow access to these additional devices without having to
add another PCI interface. A Lattice M4LV128/64 PLD decodes the
address space and provides chip selects for the devices. It also is used for
miscellaneous functions such as video blanking and sync delay and clock
drivers.

4.2.2 Video RAM (VRAM)

The display memory chips are expressly designed for high speed graphics
applications. These devices are called Video RAMs (VRAMs).
They are like ordinary DRAMs, but they also contain an internal 256 x 16
line buffer. The VRAMs have a mode control input (DT/OE), which is
used to trigger a data transfer to the line buffer. When DT/OE is active as
RAS is asserted, a data transfer cycle occurs. The row address selects a
line of data, and the column address selects the starting position within
that line. The data are then shifted out by a serial clock, 16 bits/clock
appearing at the outputs.
4-4 Troubleshooting
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