Interrupt Latency; Context Saving / Restoring; Table 2-1: Interrupt Acceptance And Levels; Table 2-2: Cycles Required For Context Saving / Restoring - Fujitsu F2MC-FR Series Application Note

Interrupt User Interrupt

2.4 Interrupt Latency

2.4.1 Context Saving / Restoring

Once the interrupt is generated and if it is enabled, "normally" the following series of steps
are performed:
1. CPU finishes current instruction execution.
2. It stores the current status to stack.
3. It fetches the starting address of the ISR from the corresponding interrupt vector.
4. And Branches to the ISR.
Steps 2 to 4 are also termed as "Context Saving".
Once the ISR execution is finished, while the execution of RETI instruction the following step
is performed:
1. The status is retrieved from the stack.
2. CPU starts executing the code which it was executing at the time of interrupt.
Steps 1 and 2 are also termed as "Context Restoring".
The time taken for the Context Saving and Context Restoring is dependent on:
Location of Stack (Internal RAM / External RAM)
Location of Interrupt Vector (Internal Flash / External Flash)
Location of Interrupt Service Routine (Internal Flash / External Flash)
Read Wait States in case of internal flash
Address indicated by stack pointer
If we consider that the internal RAM is used for stack, internal Flash is used for vector as
well as routines and internal flash wait state is 4 then the cycles required for context
saving/restoring are:
Cycle Required
Context Saving
Context Restoring
These timing gets worsened if the stack / interrupt vector / ISRs are located in the external
memory. This is because the wait cycles for external bus transfer get added to the above
mentioned cycles.
MCU-AN-300055-E-V10
INTERRUPTS
Chapter 2 Interrupt Types
16onwards As
configured
by the
correspondi
ng ICR
(Interrupt
Control
Register),
Between
Level 16
(Highest) to
31
(Disabled)

Table 2-1: Interrupt Acceptance and Levels

Address Indicated by Stack Pointer
4bytes alignment
19 CLKB cycles
9 CLKB cycles

Table 2-2: Cycles Required for Context Saving / Restoring

Current instruction
execution is finished
String instruction is
Interrupted
If ILM of PS register is
greater than interrupt
level of the peripheral
configured by ICR
and I flag of CCR is 1
For multiple requests
with same interrupt
level, smallest
interrupt number is
accepted.
2 Byte alignment
20 CLKB cycles
9 CLKB cycles
- 10 - © Fujitsu Microelectronics Europe GmbH
execution, Coprocessor ISR
can be interrupted by NMI,
Undefined Instruction, Step
Trace Trap and INTE
Instruction
Branch to interrupt vector
Save CPU status to system
stack
S = 0 (use system stack)
ILM = ICR i.e. peripheral ISR
can be interrupted by all EITs
with lower value of IL (i.e. with
higher priority)
Branch to interrupt vector