The Circuit „Interface Unit - AVT MAGIC DAB Hardware/Software Description

Eti audio decoder
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S y s t e m
D e s c r i p t i o n
PAG E 1 6
4.1
The circuit „Interface Unit"
The Interface Unit provides the data multiplexing, the generation and the
processing of the ETI protocol, as well as the monitoring of the ISO/MPEG
coded audio signals and the control of the network interface.
A multiplexing frame in the E1/2-Mbit signal consists of 32 time slots, each
with 8 bits. The frame length is 125µs (the frame frequency is 8-kHz). The
frame structure is displayed in the following diagram:
FIG. 3
0 1 2 3 4
Time slot
X 0 0 1
Frame alignment word
D-Bit:
Urgent alarm on the Remote Site
N-Bit:
Non urgent alarm on the Remote Site
Y1...Y4: National User Bits
X:
International User Bits
Time slot contains alternately the frame alignment signal and the service dig-
its. The frame alignment signal is for synchronisation, whereas the service dig-
its transmit alarms to the remote end. Time slot 16 is for the transmission of
dialling information and cannot be used for the transport of data.
Two different frame formats have been defined for 2-Mbit/s data stream:
– the Double-Frame format
– the CRC4-Multi-Frame format
The Double-Frame format corresponds exactly with FIG. 3. In the CRC4-Multi-
Frame format, a so called check bit is transmitted as the first bit of the frame
alignment word.
The ETI(NA,G.704) signal is transmitted in time slots 1...15 and 17...31.
The ETI(NI, G.703) signal is tranmitted in time slots 0...31.
The electrical characteristic of the E1 signal is according ITU G.703.
FIG. 4 shows the block diagram if the Interface Unit. central elements are the
ETI processing component and the Demux DSP.
The ETI DSP is responsible for the control of the complete signal and for the
evaluation of the ETI signal.
The Demux DSP is responsible for the complete data multiplexing. The use of
programmable logic devices permits the realisation of flexible implementa-
tions.
The PLL circuit supports all necessary clock signals such as the 48-kHz sam-
pling clock for the Audio Decoder.
MULTIPLEX FRAME OF THE 2-MBIT/S SIGNAL (E1)
Frame 125 µs
28 29 30 31
1 0 1 1
X 1 D N
Frame signalling word
0 1 2 3 4
Y1Y2Y3Y4

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