User Leds And I/O Grid - Atmel AT91CAP9A-DK User Manual

Table 7-3. PISMO-FPGA Signal Assignment (Continued)
PISMO Standard PISMO
Pin Name
H36 DNU2
H37 SM_CS3#
H38 SM_CS2#
H39 SM_CS1#
H40 SM_CS0#
7.7.5

User LEDs and I/O Grid

The 1.27 mm spaced I/O grid gathers miscellaneous yet unused FPGA signals. The user must be aware
that some of these signals share configuration functions and therefore may be active at boot time.
Note also the four signals that drive the user LEDs
UGRID55 (LED DS2 - left)
UGRID56 (LED DS3)
UGRID57 (LED DS4)
UGRID58 (LED DS5 - right)
The grid matrix assignment is as follows:
Column A = UGRID00.. 09 (A0 = UGRID00.. A9 = UGRID09)
Column B = UGRID10..19
Column C = UGRID20..29
Column D = UGRID30..39
Column E = UGRID40..49
Column F = UGRID50..59
Column G = UGRID60..69
Column H = UGRID70..75, 3.3V, 3.3V, GND, GND
Table 7-4. I/O Grid
FPGA Bank Pin Name
B8 IO
B8 IO
B8 IO
B8 IO
B8 IO
B8 IO
B8 IO
B8 IO
B12 IO
B12 IO
B12 IO
AT91CAP9A-DK Development Kit User Guide
Board Signal Name
n.c.
PISMO_SM46
PISMO_SM45
PISMO_SM44
PISMO_SM43
Alternate Function
PLL12_FBn/OUT2n
PLL12_FBp/OUT2p
PLL12_OUT1n
FPGA Pin
M7
J1
J2
N6
Configuration Function
CS
CLKUSR
nWS
nRS
RUnLU
DEV_OE
DEV_CLRn
nCS
Alternate FPGA
Pin Function FPGA Bank
DIFFIO_TX77n 5
DIFFIO_RX78p 5
DIFFIO_RX78n 5
DIFFIO_TX78p 5
Board Signal Name FPGA Bank
AC22 UGRID00
AD23 UGRID01
AE23 UGRID02
AF23 UGRID03
AG17 UGRID04
AH17 UGRID05
AG19 UGRID06
AG18 UGRID07
AL19 UGRID08
AM19 UGRID09
AH18 UGRID10
6321B–CAP–02-Jul-07
7-21