Host Usb Port; Fpga Connections; Fpga Banking Allocations; Cap/Mpio Bus Connections - Atmel AT91CAP9A-DK User Manual

For technical details, please refer to the appended schematics:
U6) and sheet 14 (look for regulator U10)
7.6

Host USB Port

The mini-AB connector J16 is connected directly to the AT91CAP9 chip. Please refer to the appended
schematics:
7.7

FPGA Connections

7.7.1

FPGA Banking Allocations

As shown in the synoptic in
schematic in Section 16)",
ered separately, thereby allowing different signaling standards of a system to be implemented in parallel.
Banking Allocations:
Banks 1, 2 and 3 = user IO going down to motherboard for user extension (PCI64, "Mistral"
connection, USB device interfaces)
Banks 4, 5 and 6 (partly) = PISMO-II extension connector
Bank 6 (partly) = leftovers allocated between the user I/O grid and EBI/FPGA connector
Bank 7 = EBI/FPGA connector
Bank 8 = AT91CAP9 connection via MPIO bus.
7.7.2

CAP/MPIO Bus Connections

Table 7-1. MPIO-FPGA Signal Assignment
CAP/MPIO Signal
MPIOA00
MPIOA01
MPIOA02
MPIOA03
MPIOA04
MPIOA05
MPIOA06
MPIOA07
MPIOA08
MPIOA09
MPIOA10
MPIOA11
MPIOA12
MPIOA13
AT91CAP9A-DK Development Kit User Guide
Section 16, sheet 7 for in-depth details of its implementation.
Figure 7-1 "AT91CAP9A-DKZ Mezzanine Block Diagram (see the complete
the Altera component has eight different IO banks. Each of these can be pow-
FPGA Pin
AG25
AB21
AE22
AF22
AD22
AH28
AK29
AJ28
AM29
AL29
AK28
AC21
AG21
AK27
Section 16, sheet 5 (look for regulator
Alternate Pin Function
DQ17B
DQSn17B
DQ17B
DQ17B
DQ17B
DQS17B
DQ16B
FPGA Bank
8
8
8
8
8
8
8
8
8
8
8
8
8
8
7-5
6321B–CAP–02-Jul-07