Table of Contents
Advertisement
8
COMMUNICATION
DTXD
DTXD
DRXD
J23
DRXD
CANTX
CANTX
CANRX
J24
CANRX
PC12
CANRS
D
HDMA
HDMA
HDPA
HDPA
J26
HDMB
HDMB
HDPB
HDPB
ETXCK
5V
TX_CLK
3V3
ETX1
GND
TXD1
ETX0
TXD0
ETXEN
TX_EN
ERX1
RXD1
ERX0
RXD0
ERXDV
RX_DV
ERXER
RX_ER
EMDC
MDC
J21
EMDIO
MDIO
PB11
MDINTR
NRST
page 7, 8
NRST
SOUND & ADC
TWD
5V
L3DATA
TWCK
3V3
L3CLOCK
C
GND
PCK1
SYSCLK
J35, J36
WS
BCK
DATAI
DATAO
EXTCLK
AC97FS
SYNC
AC97CK
BITCLK
J30, J31,J32
AC97TX
SDATA_OUT
AC97RX
SDATA_IN
NRST
RST#
ADC1
ADC2
J33
ADC3
ADC4
page 10,11,12
B
SERIAL DEVICES
PC20
MCI0_CD
MCI0_DA0
MCI0_DA0
MCI0_DA1
J28
MCI0_DA1
MCI0_DA2
MCI0_DA2
MCI0_DA3
MCI0_DA3
MCI0_CDA
MCI0_CDA
MCI0_CK
MCI0_CK
PC21
MCI1_CD
MCI1_DA0
MCI1_DA0
MCI1_DA1
MCI1_DA1
MCI1_DA2
J29
MCI1_DA2
MCI1_DA3
MCI1_DA3
MCI1_CDA
MCI1_CDA
MCI1_CK
MCI1_CK
TWD
SDA
TWCK
SCL
ISI_D[0..11]
3V3
ISI_D[0..11]
page 9
2V5
ISI_MCK
1V8
ISI_MCK
ISI_VSYNC
GND
ISI_VSYNC
ISI_HSYNC
A
ISI_HSYNC
ISI_PCK
ISI_PCK
PA14
CTRL1
PA15
CTRL2
VDDIOP1
VDDIOP1
8
7
6
TP5
TP5
TP6
TP6
TP7
TP7
TP8
TP8
TP9
TP9
TP10
TP10
5016
5016
5016
5016
5016
5016
5016
5016
5016
5016
5016
5016
J1-1
J1-1
TF0
TF1
1
3
J1-2
J1-2
TK0
TK1
4
6
WS
BCK
J1-3
J1-3
DATAI
TD0
TD1
7
9
DATAO
J1-4
J1-4
RD0
RD1
10
12
J3-1
J3-1
AD0
AD4
1
3
J3-2
J3-2
AD1
AD5
4
6
J3-3
J3-3
AD2
AD6
7
9
J3-4
J3-4
AD3
AD7
10
12
(PA0/SPI0_MISO)
(PA3/SPI0_NPCS1)
(PA4/SPI0_NPCS1)
(PA5/SPI0_NPCS0)
(PA1/SPI0_MOSI)
(PA2/SPI0_SPCK)
SPI0_MISO
SPI0_MOSI
SPI0_SPCK
MCI1_CK
MCI1_CDA
MCI1_DA0
MCI1_DA1
MCI1_DA2
MCI1_DA3
7
6
5
4
TP11
TP11
TP12
TP12
TP13
TP13
TP14
TP14
TP15
TP15
5016
5016
5016
5016
5016
5016
5016
5016
5016
5016
ATX POWER SUPPLY
12V
5V
J4
3V3
2V5
page 2
1V8
1V2
SHDN
GND
-12V
MEZZANINE CONNECTORS
FPGA[0..275]
SHDN
FPGA[0..275]
WKUP
PA[0..31]
PA[0..31]
5V
3V3
PB[0..31]
PB[0..31]
2V5
1V8
PC[0..31]
PC[0..31]
1V2
GND
PD[0..31]
PD[0..31]
VCCIO1
HDMA
HDMA
VCCIO2
HDPA
HDPA
VCCIO3
HDMB
HDMB
HDPB
HDPB
VDDIOP1
NRST
VDDIOP1
NRST
J6, J7
page 3
CAP9 PIO USAGE
PA[0..31]
PB[0..31]
PC[0..31]
PA0
PA0
MCI0_DA0
PB0
TF0
PC0
PA1
PA1
MCI0_CDA
PB1
TK0
PC1
PA2
PA2
MCI0_CK
PB2
TD0
PC2
PA3
MCI0_DA1
PB3
RD0
PC3
PA4
MCI0_DA2
PB4
TWD
PC4
PA5
MCI0_DA3
PB5
TWCK
PC5
PA6
AC97FS
PB6
TF1
PC6
PA7
AC97CK
PB7
TK1
PC7
PA8
AC97TX
PB8
TD1
PC8
PA9
AC97RX
PB9
RD1
PC9
PA10 PWM1
PB10 PCK1
PC10 LCDD6
PA11 PWM3
PB11
(ETH_MDINTR)
PC11 LCDD7
PA12 CANTX
PB12
PC12
PA13 CANRX
PB13 AD0
PC13
PA14
(ISI_CTRL1)
PB14 AD1
PC14 LCDD10
PA15
(ISI_CTRL2)
PB15 AD2
PC15 LCDD11
PA16
PA16 ISI_D0
PB16 AD3
PC16 LCDD12
PA17
PA17 ISI_D1
PB17 AD4
PC17 LCDD13
PA18
PA18 ISI_D2
PB18 AD5
PC18 LCDD14
PA19
PA19 ISI_D3
PB19 AD6
PC19 LCDD15
PA20
PA20 ISI_D4
PB20 AD7
PC20
PA21
PA21 ISI_D5
PB21 ETXCK
PC21
PA22 ISI_D6
PB22 ERXDV
PC22 LCDD18
PA23 ISI_D7
PB23 ETX0
PC23 LCDD19
PA24 ISI_PCK
PB24 ETX1
PC24 LCDD20
PA25 ISI_HSYNC
PB25 ERX0
PC25 LCDD21
PA26 ISI_VSYNC
PB26 ERX1
PC26 LCDD22
PA27 ISI_MCK
PB27 ERXER
PC27 LCDD23
PA28 ISI_D8
PB28 ETXEN
PC28 PWM0
PA29 ISI_D9
PB29 EMDC
PC29 PWM2
PA30 ISI_D10
PB30 EMDIO
PC30 DRXD
PA31 ISI_D11
PB31
PC31 DTXD
5
4
3
VCCIO1
VCCIO2
VCCIO3
J2
J2
SPI0_NPCS2
SPI0_NPCS3
1
3
PD[0..31]
(LCD_PCI)
PD0
SPI0_NPCS2
LCDHSYNC
PD1
SPI0_NPCS3
LCDDOTCK
PD2
LCDDEN
PD3
PD4
(LCD_IRQ)
(LCD_BUSY)
PD5
LCDD2
PD6
(KBD0)
LCDD3
PD7
(KBD1)
LCDD4
PD8
(KBD2)
LCDD5
PD9
(KBD3)
4X4 KEYPADS
PD10
(KBD4)
PD11
(KBD5)
PD12
(CANRS)
(KBD6)
PD13
(KBD7)
PD14
PD15
PD16
PD17
PD18
PD19
PD20
(MCI0_CD)
(MCI1_CD)
PD21
PD22
PD23
PD24
PD25
PD26
PD27
PD28
PD29
PD30
PD31
3
2
1
FPGA CONNECTORS
12V
FPGA[0..275]
FPGA[0..275]
5V
GND
-12V
NRST
NRST
VCCIO1
VCCIO2
page 4
VCCIO3
FPGA UPSTREAM
J12
3V3
GND
FPGA[0..275]
J14
FPGA[0..275]
VCCIO3
J16
page 5
LCD & TSC
LCDD[2..7]
R[0..5]
3V3
LCDD[10..15]
G[0..5]
GND
LCDD[18..23]
B[0..5]
LCDHSYNC
HSYNC
LCDDOTCK
DCLK
LCDDEN
DTMG
PWM0
VCTRL
PC0
PCI
SPI0_MOSI
MOSI
SPI0_MISO
MISO
SPI0_SPCK
SPCK
NPCS
PC4
page 13
IRQ
PC5
BUSY
UI & PIO CONNECTORS
PA[0..31]
PA[0..31]
3V3
GND
PB[0..31]
PB[0..31]
PC[0..31]
PC[0..31]
PD[0..31]
PD[0..31]
PD[6..13]
KBD[0..7]
PWM3
USERLED2
PWM1
page 6
USERLED1
PWM2
PWRLED
B
B
B
JPG
JPG
JPG
24-APR-07
24-APR-07
24-APR-07
XX-XXX-XX
XX-XXX-XX
XX-XXX-XX
A
A
A
INIT EDIT
INIT EDIT
INIT EDIT
JPG
JPG
JPG
27-OCT-06
27-OCT-06
27-OCT-06
XXX
XXX
XXX
REV
REV
REV
MODIF.
MODIF.
MODIF.
VER.
VER.
VER.
DATE
DATE
DATE
DES.
DES.
DES.
DATE
DATE
DATE
SCALE
SCALE
SCALE
1/1
1/1
1/1
REV.
REV.
REV.
SHEET
SHEET
SHEET
AT91CAP-DKM
AT91CAP-DKM
AT91CAP-DKM
1
1
1
B
B
B
DIAGRAM
DIAGRAM
DIAGRAM
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
2
1
D
C
B
A
13
13
13
Advertisement
Chapters
Table of Contents
