Digital Io Expansion Header J2100 (23); Table 13. Digital Io Expansion Header J2100 Pinout - Lantronix Intrinsyc Open-Q 865XR SOM User Manual

PCIe USB Enable DIP Switch (6). If the DIP switch is closed, the USB 3.1 Type A connector
J2300 (5) is not functional.
Pin 25 of the M.2 Socket connects to GPIO_117. GPIO_117 is shared with general purpose user
•
button (see section 3.7.7). Concurrent usage of both the user button and M.2 socket may not be
possible.
3.7.17

Digital IO Expansion Header J2100 (23)

The Open-Q 865XR SOM Development Kit includes a digital IO expansion header J2100 which provides
access to a selection of SOM GPIO signals and power rails. See item 23 in Figure 1 for the carrier board
location of this header. The pinout for this header is shown in the table below.
Pin
Signal
No
1 No Net
GPIO_41_QUP14_FP_S
3
PI_MOSI
GPIO_40_QUP14_FP_S
5
PI_MISO
GPIO_43_QUP14_FP_S
7
PI_CS
GPIO_42_QUP14_FP_S
9
PI_CLK
11 No Net
GPIO_57_QUP18_SPI_
13
MOSI
GPIO_56_QUP18_SPI_
15
MISO
17 GND
Open-Q 865XR SOM Development Kit User Guide

Table 13. Digital IO Expansion Header J2100 Pinout

Description
No Net
CPU
GPIO41/QUP1
4
CPU
GPIO40/QUP1
4
CPU
GPIO43/QUP1
4
CPU
GPIO42/QUP1
4
No Net
CPU
GPIO57/QUP1
8
CPU
GPIO56/QUP1
8
System
Ground
3: Open-Q 865XR SOM Development Kit
Pin
Signal
No
2 VREG_S4A_1P8
4 MB_VREG_3P3
6 PM8150L_GP10_PWM
GPIO_9_QUP4_CAM_S
8
PI1_MOSI
GPIO_8_QUP4_CAM_S
10
PI1_MISO
GPIO_11_QUP4_CAM_
12
SPI1_CS0_N
GPIO_10_QUP4_CAM_
14
SPI1_CLK
GPIO_59_QUP18_SPI_
16
CS_N
GPIO_58_QUP18_SPI_
18
CLK
Description
SOM LDO Regulator S4A
+1.8V
Carrier board switching
regulator. 3.3V
PM8150L GPIO10
CPU GPIO9/QUP4
CPU GPIO8/QUP4
CPU GPIO11/QUP4
CPU GPIO10/QUP4
CPU GPIO59/QUP18
CPU GPIO58/QUP18
32