Xycom XVME-400 Manual page 44

XVME-400/40l/490/491 Manual
October, 1989
*
This routine will initialize the specified SCC channel to asynchronous
*
operation. A hardware reset is assumed before code is executed.
*
*
IN: A0.1 = SCC Control Register Address
*
D7.W = [ WR13 I WR12 ] Baud Rate Time Constant
*
*
OUT:
*
All channel interrupts disabled.
*
IACK Vector Register set to $40, MIE bit set, DLC bit reset.
*
Variable IACK Vector enabled, low status
*
Xl6 Clock mode, 1 stop bit, odd parity enabled
*
Transmitter and receiver set to 8 bits/character
*
No auto enables
*
DTR/TR and RTS/RS asserted
*
Receive clock, transmit clock, and TXC/TT programed for
*
BRG Output
*
BRG clock = PCLK
*
*********************************************************************************
ASYNC-INIT:
M0VE.B
M0VE.B
M0VE.B
M0VE.B
M0VE.B
M0VE.B
M0VE.B
M0VE.B
M0VE.B
M0VE.B
M0VE.B
M0VE.B
M0VE.B
M0VE.B
M0VE.B
M0VE.B
Transmitter and receiver enabled.
#4,(A0)
#%01000101,(A0)
#3,(A0)
#$l 1 OOOOOO,(AO)
#5,(A0)
#%11l000l0,(A0)
#1,(A0)
#%01000100,(A0)
#9,(A0)
#%00001001,(A0)
#l0,(A0)
#l0,(A0)
#l l,(A0)
#%0l0l0l l0,(A0)
*
Set WR4: Xl6 clock, 1 stop bit
*
Odd parity enabled
*
Set WR3: 8 RX bits
*
No auto enable, RX disabled
*
Set WR5: DTR & RTS asserted,
8 TX bits, TX disabled
*
*
Set WRI: DMA/WAIT pins,
RX, TX, EXT INT disabled,
*
*
Parity = Special condition
WR2
*
*
IACK Vector = $40
*
Set WR9: Status Low, MIE set,
DLC=O, IACK Vector variable
*
* Set WRl0 to NRZ
l i t Set WRll: No XTAL,
* RX, TX Clock = BRG,
*
TRXC = BRG
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