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Xycom XVME-560 Manual

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Summary of Contents for Xycom XVME-560

  • Page 6 Chapter Three - Programming -- Presents information required to program operating modes, access data, and perform module calibration. The appendices at the rear of this manual provide information on XYCOM's Standard I/O Architecture, VMEbus connector/pin description, module schematics and a quick reference of module addresses and jumpers.
  • Page 8 Control/Status Module identification information Pass and Fail LED indicators The XYCOM Non-Intelligent Kernel is described in further detail in Appendix A. FEATURES OF XYCOM’S STANDARD I/O ARCHITECTURE The AIN and all XYCOM modules conform to the unique XYCOM VMEbus Standard Architecture.
  • Page 9 Module Identification - The AIN has I.D. information which provides its name, model number, manufacturer and revision level at a location that is consistent with other XYCOM I/O modules. A detailed description of XYCOM I/O Architecture is presented in Appendix A at the rear of this manual. 1.5 SPECIFICATIONS...
  • Page 10 XVME-560 Manual September, 1984 Accuracy 12 bits Resolution Linearity Differential Linearity System Accuracy of FSR with Gain = 1 with Gain = System Accuracy Temperature Drift 74db CMRR min. Monotonicity guaranteed 50 uSec Conversion time 20K conversions/sec Throughput Delay from External...
  • Page 11 XVME-560 Manual September, 1984 Shock 30 g peak acceleration, Operating 11 msec duration 50 g peak acceleration, Non-Operating 11 msec duration Physical Specifications Double Height VME board 233.35 mm x 160 mm (9.2” x 6.3”) Fully compatible with VMEbus standard...
  • Page 12 -- Data Transfer Bus Arbiter -- System Clock driver -- System Reset driver time-out module An example of such a controller subsystem is the XYCOM XVME-010 System Resource Module (SRM). OR - - A host processor which incorporates an on-board controller subsystem.
  • Page 13 XVME-560 Manual September, 1984 Analog to Digital Conversion Options The channel configuration, either single-ended inputs or differential inputs. Selected by jumpers J10, Jll, J13, J14. One of the five different input scaling ranges. Selected by jumpers J5, J6, J7, J8, and J9.
  • Page 16 XVME-560 Manuai September, 1984 2.4.2 Address Space Selection The user is given the option of placing the AIN in VMEbus Short I/O or Standard Memory Space. The selection is made by configuring jumper J2 and Switch 8 of Switch Bank 2 (see Figure 2-2) as shown in Table 2-3 below.
  • Page 17 XVME-560 Manual September, 1984 2.4.3 Supervisor/Non-Privileged Mode Selection The AIN be configured to respond to only Supervisory access, or to both Non- Privileged and Supervisory accesses, by selecting the position of Switch 7 (located in Switch Bank 2, see Figure 2-2), as shown in Table 2-4 below.
  • Page 18 XVME-560 Manual September, 1984 2.405 IACKIN/IACKOUT Daisy Chain The AIN has the ability to generate a VMEbus interrupt. Therefore, jumper J1 is hardwired in position "B" to enable the IACKIN/IACKOUT daisy chain. CAUTION The jumper shorting IACKIN to IACKOUT for the AIN’s slot in the backplane must be removed, or the...
  • Page 19 XVME-560 Manual September, 1984 Table 2-6. Interrupt Level Options Switches Level No Level selected Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 NOTE Open = "1" Logic Closed = Logic " 0 " 2.4.7 BGxIN/BGxOUT Daisy chain The Data Bus Arbitration signals BGxIN and BGxOUT (where "...
  • Page 20 XVME-560 Manual September, 1984 Analog to Digital Conversion Options 2.4.9 Channel Configuration Jumpers The AIN can operate in either single-ended or differential mode. In differential mode, the AIN converts the analog voltage difference between two inputs. In single-ended mode, the AIN converts the analog voltage on one channel with respect to Analog Ground.
  • Page 22 XVME-560 Manual September, 1984 Table 2-10. Grounding Jumper Options Input Jumpers Jumpers Mode Inserted Removed Single-ended Differential 2-11...
  • Page 24 XVME-560 Manual September, 1984 2.5.1 Signal Interface Data The inputs have been designed so that they will not be damaged if connected to long signal leads which are left open circuited. The inputs are also protected against damage if power is removed while signals are still present.
  • Page 25 Ext Trigger 2.6 MODULE INSTALLATION The XYCOM VMEbus modules can accommodate typical VMEbus backplane construc- tion. Figure 2-6 shows a standard VME chassis and a typical backplane configuration. There are two rows of backplane connectors depicted (i.e., the Pl backplane and the P2 backplane).
  • Page 26 XVME-560 Manual September, 1984 2.6.1 Installation Procedure CAUTION Do not attempt to install or remove any boards to the bus and all before turning off the power related external power supplies. Prior to installing a module, determine and verify all relevant jumper configurations and all connec- tions to external devices or power supplies.
  • Page 28 XVME-560 Manual September, 1984 Chapter 3 PROGRAMMING 3.1 INTRODUCTION This chapter provides the information required to program the AIN, access conversion data and perform calibration. This information is presented in the following fashion: Discussion of base addressing and I/O module address space...
  • Page 31 Red LED A logic “1” turns on the Green LED (Dl) will indicate the following The LEDs status (Table 3-2) set forth by the XYCOM architecture (described in Appendix Table 3-2. Status Green Module O F F operational Passed...
  • Page 35 XVME-560 Manual September, 1984 3.6 DATA ACCESS LOCATIONS The A/D converter produces a digital output which corresponds with the applied analog input at the selected channel. The digital output is stored at locations base+86H (high byte) and base+87H (low byte).
  • Page 36 XVME-560 Manual September, 1984 Table 3-6. Examples of -5 to +5 Volt Input Range Encoded in Offset Binary (a) and Two’s Complement (b) Offset Binary High Byte Low Byte 4095 +Full scale 0 0 0 0 1 1 1 1...
  • Page 37 XVME-560 Manual September, 1984 Random Channel Mode 3.7.1 In the Random Channel mode, a conversion will automatically start after a channel number is written to the Channel/Gain register. Procedure Write the control word to the control register (base+8lH) specifying bits M1 and MO as 1 and 0.
  • Page 38 XVME-560 Manual September, 1984 Mode 3.7.4 External Trigger The External Trigger mode will allow a low going pulse on pin 50 of connector start a conversion. Figure 3-5 below shows the timing constraints. Rising edge triggers conversion 100 nsec. minimum Figure 3-5.
  • Page 40 XVME-560 Manual September, 1984 Test point 1 is to be offset nulled to within +30 uV with a digital voltmeter with at least 10 uV resolution. T e s t point 1 is the output of the instrumentation amplifier which will go to the positive side of the voltmeter.
  • Page 41 (base address + 1) to (base address + 3FH) in the odd bytes only (see Figure 3- 1). The AIN uses the XYCOM module identification scheme which provides a unique method of storing module specific information in an ASCII encoded format. The I.D.
  • Page 43 The I/O Kernel -- How intelligent the operation of all XYCOM I/O modules. MODULE ADDRESSING All XYCOM I/O modules are designed to be addressed within the VMEbus-defined 64K short to the short I/O address space. The restriction of I/O modules address space provides separation of program/data address space and the address space.
  • Page 44 XVME-560 Manual September, 1984 XVME base addresses in 1K (400H) increments. On an intelligent module, address Al0-A13 Al4 and A15 signals decoded, while must be zero. (This implies that only the lowest 16 of the possible 64 segments are used for intelligent modules.) On...
  • Page 45 XVME-560 Manual September, 1984 Standardized Module I/O Map The 1K block of short I/O addresses (called the I/O Interface Block) allocated to each XVME module is mapped with a standardized format in order to simplify programming and data access. The locations of frequently used registers and module-specific For exam ple, the module identification identification information are uniform.
  • Page 49 XVME-560 Manual September, 1984 The module status/control register (found at module base address + 8lH) on intelligent XVME I/O modules provides the current status of the module self-test in conjunction The status register on intelligent with the current status of the front panel LEDs.
  • Page 51 Communication Protocol is thoroughly explained in Chapter 3 of this manual. THE KERNEL To standardize its XVME I/O modules, XYCOM has designed them around " k e r n e l s " common from module to module. Each different module type consists of a standard kernel, combined with module-dependent application circuitry.
  • Page 53 September, 1984 Appendix B VMEbus CONNECTOR/PIN DESCRIPTION The XVME-560 module is physically configured as a non-expanded (NEXP), double- height, VMEbus compatible board. There is one 96-pin bus connector on the rear edge of the board labeled P1 (refer to Chapter 2, Figure 2-l for the location). The pin connections for P1 contain the standard address, data, and control signals necessary for the operation of NEXP modules.
  • Page 54 XVME-560 Manual September, 1984 Table B-l. Pl - VMEbus Signal Identification (cont’d) Connector Signal Mnemonic Pin Number Signal Name and Description 24-31) A24-A3 1 2B: 4-11 ADDRESS bus (bits - Three-state driven bus expansion address lines. BUS BUSY - Open-collector driven signal gener-...
  • Page 55 XVME-560 Manual September, 1984 Table B-l. Pl - VMEbus Signal Identification (cont’d) Connector Signal Pin Number Signal Name and Description Mnemonic DTACK* 1A: 16 DATA TRANSFER ACKNOWLEDGE - Open- collector driven signal generated by a DTB slave. The falling edge of this signal indicates that valid...
  • Page 56 XVME-560 Manual September, 1984 Table B-1. Pl - VMEbus Signal Identification (cont’d) Connector Signal Signal Name and Description Mnemonic Pin Number SYSCLK 1A: 10 SYSTEM CLOCK - A constant 16-MHz clock signal that is independent of processor speed or timing.
  • Page 57 XVME-560 Manual September, 1984 BACKPLANE CONNECTOR Pl The following table lists the PI pin assignments by pin number order. (The connector consists of three rows of pins labeled rows A, B, and C.) Table B-2. PI Pin Assignments Row B Row C .
  • Page 67 XVME-560 Manual September, 1984 Appendix D QUICK REFERENCE GUIDE EVEN Base + OOH Module Reserved Identification Data Undefined Status/Control Interrupt Vector Channel/Gain Data High Byte Data Low Byte Undefined 3FEH 3FFH...
  • Page 68 XVME-560 Manual September , 1984 Table D-l. AIN Jumper/Switch List Jumper/Switch Enables IACKIN*/INACKOUT* daisy chain (always installed). Memory mapped operation. Short I/O operation. These jumpers select the kind of digital code that will be produced as a result of reading an analog signal (see Table 2-9).
  • Page 69 XVME-560 Manual September, 1984 Table D-2. Interrupt Level Options Switches Level No Level selected Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 NOTE Open = Logic "1" Closed = Logic " 0 "...