Xycom XVME-400 Manual page 33

XVME-400/40l/490/491 Manual
October, 1989
FIFO, the Receive Character Available IACK vector will be acquired. If there is a special
receive condition associated with the character on top of the FIFO, the Special Receive
Condition IACK vector will be acquired.
There are four special receive conditions:
Receive overrun
1)
Framing error (ASYNC only)
2)
End of frame (SLDLC only)
3)
Parity error (if WRl:D2=1)
4)
For interrupt driven operation, it is suggested that an interrupt on all receive characters
or special conditions be programmed along with programming parity errors as a special
condition. When programmed in this mode, and the receive character available IACK
vector is acquired, it is guaranteed that no special conditions exist for the received byte
on top of the FIFO. Therefore, RR1 does not have to be checked after every receive byte.
This eliminates two VMEbus cycles from the receive character interrupt service routine.
When a special receive condition IACK vector is acquired, the following sequence should
be executed in the specified order:
1) Read RR1 to determine the source of special condition.
Issue reset error command in WRO to clear errors.
2)
Read the data register.
3)
3.3.2 Transmit Buffer Empty Interrupts
Each of the four channels has its own Transmit Character available: IE, IP, and IUS
internal bits. The IE bit is set (i.e., transmit buffer interrupts are enabled) by setting
WRl:Dl. If these interrupts are enabled, two events can cause this IP to become set: when
the transmit buffer is ready to receive a byte (RRO:D2=1),
synchronous modes (RRO:D2=0).
issuing the Reset TxINT Pending command WRO.
3.3.3 External/Status
There are six sources of interrupts that share this IP:
Break/Abort
1)
Underrun/EOM
2)
C T S
3)
D C D
4)
Sync/Hunt
5)
Zero Count
6)
Each of these sources has a separate enable bit in WR15 and has a separate status bit in
RRO. The master external/status interrupt enable bit is WRl:DO. In general, when a status
bit changes state and is enabled, the external/status IP will be set and cause an interrupt.
The IP is reset by issuing the Reset External/Status Interrupt command in WRO.
The IP is reset by writing to the data register or by
Interrupts
3-5
and after the CRC is sent in