Xycom XVME-400 Manual page 41

XVME-400/40l/490/491 Manual
October, 1989
*********************************************************************************
*
*
This subroutine will initialize the specified SCC channel for asynchronous
*
operation.
*
On entry:
A0.L = SCC control register address
D7.W = [ WR13 ] WR12 ] baud rate time constant
On exit:
*
*
Transmitter and receiver enabled
*********************************************************************************
ASYNC INIT:
M0VE.B
M0VE.B
M0VE.B
M0VE.B
M0VE.B
M0VE.B
M0VE.B
M0VE.B
M0VE.B
M0VE.B
M0VE.B
M0VE.B
M0VE.B
M0VE.B
M0VE.B
M0VE.B
M0VE.B
M0VE.B
R0R.W
M0VE.B
M0VE.B
#9,(A0)
#$8O,(AO)
#4,(A0)
#%01000101,(A0)
#3,(A0)
#%11000000,(A0)
#5,(A0)
#%ll lOOOlO,(AO)
#l,(AO)
#%01000100,(A0)
#2,(A0)
#$4O,(AO)
#9,(A0)
#%00001001,(A0)
#1O,(AO)
#0,(AO)
#1l,(AO)
#%0l0l0ll0,(A0)
#8,D7
#13,(AO)
D7,(AO)
3-13
* Set WR9
* Reset channe 1 A, SCC #l
* Set WR4: X16 clock, 1 stop bit
* Odd parity enabled
* Set WR3: 8 RX bits disabled
* No auto enable
* Set WR5: DTR and RTS asserted
* 8 TX bits, TX disabled
* Set WRl: DMA/WAIT pins
* Set RX,TX, ext. int. disabled
* Parity = special condition
* Set WR2
* IACK vector = $40
* Set WR9: status o 1 w, MIE set
* DLC=O 9 IACK vector variable
* Set WRl0 to NRZ
* Set WRll: no XTAL
* RX TX clock=BRG
* TRXC=BRG
* Set WR13: High order
* Time constant