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Xycom XVME-240 Manual

Digital i/o module
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Summary of Contents for Xycom XVME-240

  • Page 6 The Appendices are designed to introduce and reinforce a variety of module-related Architecture, backplane signal/pin descrip- topics including: XYCOM’s Standard tions, a block diagram and schematics, and a quick reference section. 1.3 MODULE OPERATIONAL DESCRIPTION Figure l- 1 shows an operational block diagram of the DIO module.

  • Page 8: Specifications

    I/O modules. The central core of the XYCOM Standard I/O Architecture is the “kernel”. uses a non-intelligent kernel which provides the circuitry required to receive and generate all of the signals for a VMEbus defined 16-bit "slave”...
  • Page 9 XVME-240 Manual October, 1984 Table l-l. DIO Module Specifications Specification Characteristic 64 (arranged in 8 logical ports) Number of I/O Channels Number of Flag Output Lines Number of Interrupt Input Lines Output Characteristics - Flag Outputs: Vol Low-level output voltage 0.5V max.
  • Page 10 XVME-240 Manual October, 1984 Table l-1. DIO Module Specifications (continued) Specification Characteristic Temperature Operating Non-Operating Humidity 5 to 95% RH non-condensing (Note, extreme low humidity conditions may require special protection against static discharge.) Altitude Sea-level to 10,000 ft. (3048m) Operating Sea-level to 50,000 ft.

  • Page 11: Installation

    DIO; and a controller subsystem module which employs a Data Transfer Bus Arbiter, a Subsystem Clock driver, a System Reset driver, and a Bus time- out module. (The XYCOM XVME-010 System Resource Module provides a controller subsystem with the components listed.)
  • Page 13 Interface Block). The base address decoding scheme for XYCOM I/O modules is such that the starting address for each I/O Interface Block resides on a 1K boundary. Thus the module base address may be set to any one of 64 possible 1K boundaries within the Short I/O Address space.
  • Page 16 XVME-240 Manual October, 1984 2.4.2 Address Space Selection The user is given the option of placing the DIO in VMEbus Short I/O or Standard Memory Space. The selection is made by configuring jumper J2 and Switch 8 of Switch Bank 2 (see Figure 2-3) as shown in Table 2-3 below.
  • Page 17 XVME-240 Manual October, 1984 2.4.3 Supervisor/Non-Privileged Mode Selection The DIO can be configured to respond to only Supervisory access, or to both Non- Privileged and Supervisory accesses, by selecting the position of Switch 7 (located in Switch Bank 2, see Figure 2-3), as shown in Table 2-4 below.
  • Page 18 XVME-240 Manual October, 1984 2.4.5 IACKIN*/IACKOUT* Daisy Chain The DIO has the ability to generate a VMEbus interrupt. Therefore, jumper Jl is hardwired in position “ B " to enable the IACKIN*/IACKOUT* daisy chain. CAUTION The jumper shorting IACKIN* to IACKOUT* for the DIO’s slot in the backplane must be removed, or the...
  • Page 19 XVME-240 Manual October, 1984 Table 2-6. Interrupt Level Options Switches Level No Level selected Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 N O T E Open = "1" Logic Closed = Logic "0"...
  • Page 20 XVME-240 Manual Octo ber , 1984 Jumpers J3-J10 are all two position jumpers, with the two positions labeled " A " and "B" . Figure 2-5 shows an enlarged view of jumper Jl0 and how the two positions are labeled. The remaining 7 jumpers are all identical to jumper Jl0.
  • Page 22 XVME-240 Manual October, 1984 CAUTION Do not attempt to attach external connections with- out first removing power from the module. Table 2-8 lists the pin definitions for connectors JKl and JK2. Notice that connector JKl contains ports 0-3 and connector JK2 contains ports 4-7. Each...
  • Page 23 XVME-240 Manual October, 1984 Table 2-8. JK 1 and JK2 Pin Definitions (continued) Port Definition Pin Number CONNECTOR JK 1 Flag Output Line 2 of Flag Output (Bit Register) Data Bit 0 Data Bit 1 Data Bit 2 Data Bit 3...
  • Page 24 XVME-240 Manual October, 1984 Table 2-8. JKl and JK2 Pin Definitions (continued) Port Definition Pin Number CONNECTOR JK 2 Flag Output Line (Bit 5 of Flag Output Register) G N D G N D Data Bit 0 Data Bit 1...
  • Page 25 Pl and P2 are found in Appendix B of this manual. 2.7 DIO MODULE INSTALLATION The XYCOM VMEbus modules are designed to accommodate typical VMEbus backplane Figure 2-6 shows a standard VME chassis and a typical backplane construction.

  • Page 27: Installation Procedure

    XVME-240 Manual Octo ber , 1984 2.8 INSTALLATION PROCEDURE CAUTION Do not attempt to install or remove any boards without first turning off the power to the bus, and all related external power supplies. Prior to installing a module, you should determine and verify all relevent jumper configurations and all connections to external devices or power supplies.
  • Page 28 This chapter provides the information needed to program the DIO to perform Input and/or Output data transfers and how to use the unique design features which are a part of XYCOM I/O modules. The chapter is arranged in the following order: Module base addressing...
  • Page 30 Identification Data (Base+0lH to 3FH - odd byte locations only) The XYCOM module identification scheme provides a unique method of registering module-specific information in an ASCII encoded format. The I.D. data is provided as thirty-two ASCII encoded characters consisting of the board type, manufacturer identification, module model number, number of 1K byte blocks occupied by the module, and module functional revision level information.
  • Page 32 October, 1984 3.3.2 Module Status/Control Register (Base Address+081H) A major feature of the XYCOM Standard I/O Architecture is the inclusion of an 8-bit status and control register on all intelligent and non-intelligent I/O modules. On the DIO module (a non-intelligent module) this register provides the user with two...
  • Page 33 XVME-240 Manual October, 1984 Bit 2: Read Only This bit acts as a flag to show if there are any interrupts pending on the DIO. A logic "1" indicates that at least one interrupt is pending. A logic " 0 "...
  • Page 34 XVME-240 Manual October, 1984 in the I/O Interface Block, and if the base address of the module is set at l000H, then I/O Port 3 can be accessed at 108BH. (Module Base (I/O Interface (I/O Address) Block Offset) Port 3)
  • Page 35 XVME-240 Manual October, 1984 The Port Direction register is cleared to all "0"s (all ports are inputs) by a VME SYSRESET or by a Soft Reset (see Section 3.3.2 for information on performing a Soft Reset). Thus when the module is powered-up or when it is reset, the ports will all automatically be configured as inputs.
  • Page 36 XVME-240 Manual October, 1984 When an interrupt signal has been detected and latched by an interrupt input, the bit corresponding to that interrupt input in the Interrupt Input Register will be set to logic "1". This bit will remain set until the interrupt input latch is properly cleared by...
  • Page 37 XVME-240 Manual October, 1984 Each bit of the Interrupt Clear Register is connected to a specific interrupt input latch. By writing a "1" to a particular bit position in the Clear Register, you will clear the corresponding interrupt input latch and register. For example, if a module base...
  • Page 38 XVME-240 Manual October, 1984 INTERRUPT MASK REGISTER Base Address + 83H) Interrupt Input Latch 1 Interrupt Input Latch 2 Interrupt Input Latch 3 Interrupt Input Latch 4 Interrupt Input Latch 5 Interrupt Input Latch 6 Interrupt Input Latch 7 Writing a "1" will "pass" an interrupt.
  • Page 39 XVME-240 Manual October, 1984 Interrupts Pending register shows which interrupts in particular (input lines) are pending. As mentioned in the previous section (Section 3.3.6), the contents of the interrupt latch and the Interrupt Mask Register are logically ANDed. The Interrupts...
  • Page 40 XVME-240 Manual October, 1984 INTERRUPT VECTOR REGISTER (Base Address + 85H) L S B Figure 3-8. Interrupt Vector Register NOTE The Interrupt Vector Register powers up to an indeterminate state, and it must be programmed before interrupts are enabled. The vector register is programmed by writing the vector address to the module base address + 85H.
  • Page 41 XVME-240 Manual October, 1984 FLAG OUTPUTS REGISTER (Base Address + 86H) Flag Output 3 Flag Output 4 Flag Output 5 Flag Output 6 Flag Output 7 Writing logic " 1" = Flag Output of "1" Writing logic " 0 "...
  • Page 43 XVME-240 Manual October, 1984 The Interrupt Input signal is buffered before it reaches the Edge Detection circuitry. Depending upon how the Edge Detection Jumper is set, the Interrupt Input signal will be gated in on either its rising or falling edge (refer to Section 2,4.8). After the Interrupt Input signal is gated through the Edge Detection circuitry, it can be latched (providing the Interrupt Input latch is cleared).
  • Page 44 XVME-240 Manual October, 1984 Any interrupt Enable bit, the interrupt capability of the DIO module is disabled. Interrupt Mask while interrupts signals which are latched in and passed through the disabled will remain pending until the interrupts are enabled, cleared, or masked out.
  • Page 45 XVME-240 Manual October, 1984 Interrupt Input Register could be read to determine if there are any latched interrupts which are being “masked out". The mask can then be rewritten to allow the masked interrupts to become pending interrupts. The pending interrupts can now be serviced by the handler routine in the same fashion as shown above.

  • Page 46: Module Addressing

    Since each I/O module connected to the bus must have its own unique base address, the base addressing scheme for XYCOM VME I/O modules has been designed to be jumper- selectable. Each XVME I/O module installed in the system requires at least a 1K byte block of the short I/O memory.
  • Page 47 XVME-560 Manual September, 1984 On an intelligent XVME module, address base addresses in 1K (400H) increments. signals Al0-A13 are decoded, while Al4 and Al5 must be zero. (This implies that only the lowest 16 of the possible 64 1K segments are used for intelligent modules.) On non-intelligent modules, the six highest order short I/O address bits are XVME...
  • Page 48 XVME-240 Manual October, 1984 Standardized Module I/O Map The 1K block of short I/O addresses (called the I/O Interface Block) allocated to each XVME module is mapped with a standardized format in order to simplify programming and data access. The locations of frequently used registers and module-specific identification information are uniform.
  • Page 52 XVME-240 Manual October, 1984 The module status/control register (found at module base address + 81H) on intelligent XVME I/O modules provides the current status of the module self-test in conjunction with the current status of the front panel LEDs. The status register on intelligent modules is a “Read Only"...

  • Page 54: Interrupt Control

    Communication Protocol is thoroughly explained in Chapter 3 of this manual. THE KERNEL To standardize its XVME I/O modules, XYCOM has designed them around "kernels" common from module to module. Each different module type consists of a standard kernel, combined with module-dependent application circuitry. Module standardiza- tion results in more efficient module design and allows the implementation of the Standard I/O Architecture.
  • Page 56 October, 1984 Appendix B VMEbus CONNECTOR/PIN DESCRIPTION The XVME-240 Digital Input/Output module is physically configured as a non-expanded (NEXP), double-height, VMEbus compatible board. There is one 96 pin bus connector on the rear edge of the board labeled Pl, and one 96 pin bus connector labeled P2 (refer to Chapter 2, Figure 2-l for the locations).
  • Page 57 XVME-240 Manual October, 1984 Table B-1. VMEbus Signal Identification (cont’d) Connector Signal Pin Number Signal Name and Description Mnemonic BUS BUSY - Open-collector driven signal gener- 1B:1 BBSY* ated by the current DTB master to indicate that it is using the bus.
  • Page 58 XVME-240 Manual October, 1984 Table B-l. VMEbus Signal Identification (cont’d) Connector Signal Mnemonic Pin Number Signal Name and Description DTACK* 1A:16 DATA TRANSFER ACKNOWLEDGE - Open- collector driven signal generated by a DTB slave. The failing edge of this signal indicates that valid...
  • Page 59 XVME-240 Manual October, 1984 Table B-l. VMEbus Signal Identification (cont’d) Connector Signal Pin Number Mnemonic Signal Name and Description 1A: 10 SYSCLK SYSTEM CLOCK - A constant 16-MHz clock signal that is independent of processor speed or timing. This signal is used for general system timing use.
  • Page 60 XVME-240 Manual October, I984 BACKPLANE CONNECTOR Pl The following table lists the PI pin assignments by pin number order. (The connector consists of three rows of pins labeled rows A, B, and Table B-2. P 1 Pin Assignments Row A...
  • Page 61 XVME-240 Manual October, 1984 Table B-3. P2 - VMEbus Signal Identification Connector Signal Pin Number Signal Name and Description Mnemonic +5 Vdc Power - Used by system logic circuits. 2G: 2,12 Ground G N D 22,31 ALL OTHER PINS NOT USED BACKPLANE CONNECTOR P2 The following table lists the P2 pin assignments by pin number order.
  • Page 71 XVME-240 Manual October, 1984 Appendix D QUICK REFERENCE GUIDE Even BASE+00H Module Undefined Identification +3EH +40H Undefined +7EH Interrupt inputs Status/Control +80H +82H Pend. Interrupt Mask Interrupts +84H Interrupt Clear Interrupt Vector Flag Outputs Port Direction +86H I/O Port 0...
  • Page 72 XVME-240 Manual October, 1984 The DIO Jumpers and Switch Definitions Function Jumper Address Space selection jumper (i.e., Short I/O Address Space or Standard Address Space). J3, J4, 35, 36, J7, J8, Interrupt input edge detection option jumpers. J9 and Jl0...