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Xycom XVME-400 Manual

Quad serial i/o modules
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Summary of Contents for Xycom XVME-400

  • Page 6 The XVME-400 and XVME-401 are single-high, while the XVME-490 and XVME-491 are double-high. The XVME-400 and XVME-401 access the I/O through the JKl and JK2 connectors on the module front panel, whereas the XVME-490 and XVME-491 route their I/O to the VMEbus P2 connector.

  • Page 7: Manual Structure

    Appendix C - Block diagrams, assembly drawings, and schematics. NOTE This manual (XYCOM part # 74400-002) is part of a manual kit (XYCOM part # 74400-001) that is being shipped with the XVME-400/401/490/491 Modules. The kit also contains an 8530 Manual’...

  • Page 10: Module Specifications

    XVME-400/401/490/491 Manual October, 1989 1.4 MODULE SPECIFICATIONS The following is a list of the operational and environmental specifications for the XVME-400/40l/490/491 Modules. Table l- 1. XVME-400/40l/490/491 Module Specifications Characteristic Specification Number of Channels Serial Device Zilog 28530 Level Compatibility: XVME-400/490...
  • Page 11 XVME-400/40l/490/491 Manual October, 1989 Table l- 1. XVME-400/40 l/490/49 1 Module Specifications (cont.) Characteristic Specification Vibration 5 to 2000 Hz Operating 0.0 15” peak-to-peak displacement 2.5 g peak acceleration Non-operating 5 to 2000 Hz 0.030” peak-to-peak displacement 5.0 g peak acceleration...

  • Page 12: Installation

    Bus Timeout Module A host processor which incorporates the system controller functions on-board. An example of such a controller subsystem is the XYCOM XVME-010 System Resource Module (SRM). Prior to installing the XVME-400/401/490/491 Module, it will be necessary to configure several jumper options.
  • Page 17 Selects the VMEbus interrupt level for the module (refer to Section 2.4.3). 2.4.1 Base Address Jumpers (JA10-JA15) The XVME-400/401/490/491 Module can be configured to be addressed at any one of the 64 1 Kbyte boundaries within the VME Short I/O address space by using jumpers JAl0 through 5 (see Figures 2-1, 2-2, 2-3, and 2-4 for the location of the jumpers on the board) as shown above.
  • Page 19 Each XVME-400/401/490/491 Module has one jumper that determines which address modifier codes it respond to. This jumper is Jl on the XVME-400/490 and J7 on the will XVME-401/491 (see Figures 2-1, 2-2, 2-3, and 2-4 for the jumper location). When this jumper is in, the module will respond to supervisory short I/O bus cycles only.
  • Page 20 XVME-400/40 l/490/491 Manual October, 1989 2.4.4 +5V Power Supply (Jl, J2; XVME-401 only) On the XVME-401, jumpers Jl and J2 control whether the +5V supply is brought out to front-edge connectors JKl and JK2. Table 2-6 indicates the functions of these jumpers.
  • Page 22 XVME-400/401/490/491 Manual October, 1989 On the XVME-400/401, connector JKl carries the signals for Channels 0 and 2, while connector JK2 carries the signals for Channels 1 and 3. On the XVME-490/491, the signals for all four channels are carried on connector P2. All channels on all modules are configured as DTE.
  • Page 23 XVME-400/40l/490/491 Manual October, 1989 2.5.1.1 JKl and JK2 Connector Pinouts on the XVME-400 (RS-232C) Table 2-8 shows the XVME-400 pinout connectors JKl and JK2. These signals meet the RS-232C specifications. Table 2-8. XVME-400 Front Edge Connector Pin Definitions Number Signal...
  • Page 24 XVME-400/40l/490/491 Manual October, 1989 2.5.1.2 JKl and JK2 Connector Pinouts on the XVME-401 (RS-485/422A) Table 2-9 shows the XVME-401 pinouts for connectors JKl and JK2. These signals meet the RS-485/422A specifications. Table 2-9. XVME-401 Front Edge Connector Pin Definitions Signal...
  • Page 25 XVME 400/401/490/491 Manual October, 1989 N O T E All XVME-401 signal names are in the form “XXNZ”, where “N” is the channel number, “Z” is A or B based on the polarity of the differential signal (as defined by RS-485), and “XX”...
  • Page 26 XVME-400/40l/490/491 Manual October, 1989 Table 2-10. XVME-490 Rear Edge P2 Connector Pin Definitions (Cont’d) Pin # Row A Signal Row B Signal Row C Signal TXD2 RXD2 RTS2 RXC2 Ch. 2 C T S 2 DTR2 DCD2 TXC2 TXD3 RXD3 RTS3 RXC3 Ch.
  • Page 27 XVME-400/40l/490/491 Manual October, 1989 2.5.2.2 P2 Connector Pinouts on the XVME-491 (RS-485/422A) Table 2-11 shows the XVME-491 pinouts for connector P2. These signals meet the RS-485/422A and VMEbus specifications. T-able 2-11. XVME-491 Rear Edge P2 Connector Pin Definitions Signal Signal...

  • Page 28: Module Installation

    Manual October, 1989 MODULE INSTALLATION XYCOM XVME modules are designed to comply with all physical and electrical VMEbus backplane specifications. The XVME-400/401 Modules are single-high and single-wide and, as such, only require the Pl backplane. The XVME-490/491 Modules are double- high and single-wide, and use the PI and P2 backplane.

  • Page 29: Module Programming

    The XVME-400/401/490/491 Modules are designed to be addressed within the VMEbus- defined 64 Kbyte short I/O address space. When the XVME-400/401/490/491 Module is installed in the system it will occupy a 1 Kbyte block of the short I/O address space. The base address decoding scheme for the XVME I/O modules is such that the starting address for each board resides on a 1 Kbyte boundary.
  • Page 30 Register 1OOOH 1007H NOTE The XVME-400/401/490/491 is an odd byte only slave, and as such, the module will not respond to even address, single-byte accesses. However, word accesses may be used, with the understanding that only the odd byte of the word is used to exchange data.
  • Page 31 October, 1989 3.3 MODULE INTERRUPT SOURCES There are twelve sources of interrupts on the XVME-400/401/490/491 (three sources from each serial channel). When enabled, each of these sources can generate VMEbus interrupts on the level specified by jumpers JAI-JA3. The interrupt sources are prioritized during the VMEbus IACK cycle, as shown in Table 3-2.
  • Page 33 XVME-400/40l/490/491 Manual October, 1989 FIFO, the Receive Character Available IACK vector will be acquired. If there is a special receive condition associated with the character on top of the FIFO, the Special Receive Condition IACK vector will be acquired. There are four special receive conditions:...

  • Page 34: Clocking Options

    XVME-400/40l/490/491 Manual October, 1989 3.4 CLOCKING OPTIONS This section describes the transmit and receive clocking options for the serial channels. It applies to all four independently configurable serial channels. 3.4.1 Hardware Configurations The SCC receive clock input pin, RTXC, is driven from line receivers which are connected to the JK RT input (see Section 2.5).
  • Page 35 XVME-400/40l/490/491 Manual October, 1989 3.4.2 Baud Rate Generator The SCC contains a programmable baud rate generator whose output can be used as internal timing sources. The baud rate generator’s clock input may be programmed to connect to either the RXC/RT signal or PCLK (WR14). A 16-bit time constant can be programmed into WR13 (most significant byte) and WR12 (least significant byte) to select the baud rate generator’s output frequency.
  • Page 36 XVME-400/40l/490/491 Manual October, 1989 Table 3-4. Typical Time Constraints for Synchronous (xl) Clock Time Constant WR13 Value WR12 Value Baud Rate (Base 10) (Hex) (Hex) 76.8 K 38.4 K 19.2 K 9600 7200 4800 3600 2400 1800 1022 1200 1534...
  • Page 37 XVME-400/401/490/491 Manual October, 1989 SERIAL CHANNEL CLOCK CONFIGURATIONS The receiver and/or transmitter can be independently programmed to accept their clock source from any of the following: the RXC/RT signal, the baud rate generator, or the digital phase locked loop (see the SCC manual). (TXC/TT may not be programmed as a clock source.) The receiver option is specified in WRl l:D6,D5, the transmitter in...

  • Page 38: General Programming Considerations

    XVME-400/40l/490/491 Manual October, 1989 3.7 GENERAL PROGRAMMING CONSIDERATIONS This section outlines programming rules which apply to all modes of operation. These constraints are dictated by hardware configurations. WRl - Set D7, D6, D5 to 0, 1, 0. This will disable the DMA and WAIT features of the SCCs.
  • Page 39 XVME-400/40l/490/491 Manual October, 1989 Synchronous Operation Initialization 3.7.2 This section describes the steps required to set up the SCCs for synchronous operation. These steps apply to any channel and should be followed in the specified order. Issue the Channel Reset command (WR9:D7,6).
  • Page 40 XVME-400/40l/490/491 Manual October, 1989 3.8 PROGRAMMING EXAMPLE ******************************************************************************** XVME-400/40 l/490/49 1 Sample Program Polled mode - Asynchronous Operation EQUATES ********************************************************************************* BASE $OOFFOOOO * Base address of module S T A C K $A00 * Start of stack BASE+13 * SCC #l control register...
  • Page 41 XVME-400/40l/490/491 Manual October, 1989 ********************************************************************************* This subroutine will initialize the specified SCC channel for asynchronous operation. On entry: A0.L = SCC control register address D7.W = [ WR13 ] WR12 ] baud rate time constant On exit: Transmitter and receiver enabled...
  • Page 42 XVME-400/40l/490/49I Manual October, 1989 R0L.W * Set WR12: Low order #8,D7 M0VE.B #12,(AO) * Time constant M0VE.B D7,(AO) * Set WR14 M0VE.B #14,(AO) M0VE.B * BRG source=PCLK #2,(AO) M0VE.B #14,(AO) M0VE.B * Enable BRG #3,(A0) #15,(AO) * Set WR15: Disable all external M0VE.B...
  • Page 43 XVME-400/40I /490/491 Manual October, 1989 ******************************************************************************** This routine will receive a byte of data in polled mode. On entry: A3 contains the address of the command register of the SCC channel used for receiving. On exit: D3.B contains the byte which was received.
  • Page 44 XVME-400/40l/490/491 Manual October, 1989 This routine will initialize the specified SCC channel to asynchronous operation. A hardware reset is assumed before code is executed. IN: A0.1 = SCC Control Register Address D7.W = [ WR13 I WR12 ] Baud Rate Time Constant OUT: Transmitter and receiver enabled.
  • Page 45 XVME-400/40l/490/491 Manual October, 1989 * Set WR13 = High order R0R.W #8,D7 * Time constant M0VE.B #13, M0VE.B D7,(AO) * Set WR12 = Low Order R0L.W #8,D7 * Time constant M0VE.B #12,(AO) M0VE.B D7,(AO) * Set WR14: M0VE.B #14,(A0) * BRG source = PCLK M0VE.B...
  • Page 46 XVME-400/40l/490/491 Manual October, 1989 Appendix A VMEbus CONNECTOR/PIN DESCRIPTIONS Pl BACKPLANE CONNECTOR All the modules have the rear-edge connector PI, which is a 96-pin bus connector consisting of three rows of 32 pins each. (Row A is physically closest to the board. See Table A-2).
  • Page 47 XVME-400/40l/490/491 Manual October, 1989 Table A-l. VMEbus Signal Identification (cont’d) Connector Signal Pin Number Signal Name and Description Mnemonic 1 A:24-30 ADDRESS BUS (bits l-23): Three-state driven address lines A0I-A23 lC:15-30 that specify a memory address. 2B:4-11 ADDRESS BUS (bits 24-31): Three-state driven bus A24-A3 1 expansion address lines.
  • Page 48 XVME-400/40l/490/491 Manual October, 1989 Table A-1. VMEbus Signal Identification (cont’d) Connector Signal Mnemonic Pin Number Signal Name and Description BR0*-BR3* lB:12-15 BUS REQUEST (0-3): Open-collector driven signals generated by Requesters. These signals indicate that a DTB master in the daisy-chain requires access to the bus.
  • Page 49 XVME-400/40l/490/491 Manual October, 1989 Table A-l. VMEbus Signal Identification (cont’d) Connector a n d Signal Pin Number Signal Name and Description Mnemonic IACK* 1A:20 INTERRUPT ACKNOWLEDGE: Open-collector or three- state driven signal from any master processing an interrupt request. It is routed via the backplane to slot 1, where it...
  • Page 50 XVME-400/401/490/491 Manual October, 1989 Table A-l. VMEbus Signal Identification (cont’d) Connector Signal Mnemonic Pin Number Signal Name and Description SYSTEM FAIL: Open-collector driven signal that indicates SYSFAIL* 1C:l0 It may be that a failure has occurred in the system. generated by any module on the VMEbus.
  • Page 51 XVME-400/40 l/490/49 1 Manual October, 1989 Table A-2. Pl Signal Identification Row A Row B Row C Signal Signal Signal Mnemonic Number Mnemonic Mnemonic BBSY* D O 8 BCLR* D O 9 D O 2 ACFAIL* D O 3 BG0IN*...
  • Page 52 XVME-400/40l/490/491 Manual October, 1989 BACKPLANE CONNECTOR P2 and XVME-491 have the rear-edge connector P2, which is a 96-pin bus XVME-490 connector consisting of three rows of 32 pins each. (Row A is physically closest to the board.) Table A-3 identifies the RS-232C P2 signals for the XVME-490, while Table A-4 shows the RS-485/422A signals for the XVME-491.
  • Page 53 XVME-400/40l/490/491 Manual October, 1989 Table A-4. P2 Signal Identification for the XVME-491 Pin # Row A Signal Row B Signal Row C Signal TXDO+ v c c TXDO- TXCO- TXCO+ RTSO- RTSO+ RXDO+ Ch. 0 RXDO- RXCO+ RXCO- CTSO+ CTSO-...
  • Page 54 50-pin connectors consisting of three rows of 32 pins each. Table A-5 identifies the RS-232C signals carried by the JKl and JK2 connectors on the XVME-400. Table A-6 shows RS-485/422A signals carried by the JKl and JK2 connectors on the XVME-401.
  • Page 55 XVME-400/40l/490/491 Manual October, 1989 Table A-6. JKl and JK2 Signal Identification for the XVME-401 (RS-485/422A) Signal Signal Direction Number Signal SDOB SDlB Transmit Data SDIA Transmit Data SDOA RDOB RDlB Receive Data RDOA RDlA Receive Data RSOB RSlB Request To Send...
  • Page 56 XVME-400/401/490/491 Manual October, 1989 Output Sources of JKl /JK2. or P2 Connector Signals (one set for each serial channel) TXD/SD SCC output pin TXD drives a line driver. Driver output is sent to this pin. RTS/RS SCC output pin RTS* drives a line driver. Driver output is sent to this pin.
  • Page 57 XVME-400/40l/490/491 Manual October, 1989 Appendix B QUICK REFERENCE GUIDE Table B-l. XVME-400 and XVME-490 Jumper List Jumper Determines whether the module will respond to supervisory or supervisory and non-privileged short I/O VMEbus cycles (refer to Section 2.4.2 of this manual).
  • Page 58 XVME-400/40l/490/491 Manual October, 1989 Table B-3. Addressing Options Address Modifier to which the Jumper XVME-400/40l/490/491 Module will respond Jl (XVME-400/490) , or J7 (XVME-401/491) (2DH) Supervisory only (2DH) Supervisory or (29H) Non-privileged o u t Table B-4. Interrupt Level Jumper Positions...
  • Page 59 XVME-400/40l/490/491 Manual October, 1989 Table B-6. VMEbus Base Address Options Jumpers VME Base Address in VME JA15 JA14 JA13 JA12 JAI1 JAl0 Short I/O Address Space OOOOH 0400H 0800H OCOOH 1OOOH 1400H 18OOH 1COOH 2000H 2400H 2800H 2COOH 3000H 3400H...
  • Page 60 XVME-400/40l/490/491 Manual October, 1989 Table B-6. VMEbus Base Address Options (Cont’d) Jumpers VME Base Address in JA15 JA14 JA13 JAI2 JAI1 JAl0 I/O Address Space Short o u t o u t A800H o u t o u t o u t...

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Xvme-401Xvme-490Xvme-491